Abstract: An imaging device includes a first pixel circuit having a first plurality of photodiodes that includes a phase detection autofocus photodiode with image sensing photodiodes. A first buffer transistor having a first threshold voltage is coupled to the first plurality of photodiodes to generate a first output signal. A second pixel circuit is included having a second plurality of photodiodes that are all image sensing photodiodes. A second buffer transistor having a second threshold voltage is coupled to the second plurality of photodiodes to generate a second output signal. The first threshold voltage is less than the second threshold voltage. A driver is coupled to receive a combination of the first and second output signals to generate a total output signal. An influence of the first output signal dominates the second output signal in the total output signal because the first threshold voltage is less than the second threshold voltage.

Abstract: A pixel cell includes a photodiode buried beneath a first side of semiconductor material and coupled to photogenerate image charge in response to incident light. A transfer gate is disposed over the photodiode and includes a vertical transfer gate portion extending a first distance from the first side into the semiconductor material. A floating diffusion region is disposed in the semiconductor material proximate to the transfer gate and is coupled to transfer the image charge from the photodiode toward the first side of the semiconductor material and into the floating diffusion region in response to a transfer control signal. A first pixel transistor having a first gate is disposed over the photodiode proximate to the first side of the semiconductor material. The first gate has a ring structure laterally surrounding the floating diffusion region and the transfer gate at the first side of the semiconductor material.

Abstract: A pixel circuit includes a photodiode, a floating diffusion, and a conduction gate channel of a multi-gate transfer block disposed in a semiconductor material layer. The multi-gate transfer block is coupled to the photodiode, the floating diffusion, and an overflow capacitor. The multi-gate transfer block also includes first, second, and third gates that are disposed proximate to the single conduction gate channel region. The conduction gate channel is a single region shared among the first, second, and third gates. Overflow image charge generated in the photodiode leaks from the photodiode into the conduction gate channel to the overflow capacitor in response to the first gate, which is coupled between the photodiode and the conduction gate channel, receiving a first gate OFF signal and the second gate, which is coupled between the conduction gate channel and the overflow capacitor, receiving a second gate ON signal.

Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

Abstract: A lens-array imager includes lenses Lm forming a lens array having a pitch dx, a pixel array including pixel-array regions Rm, and apertured baffle-layers therebetween; m={0, 1, 2, . . . }. Each pixel-array region has a width rx<dx and pitch px<dx. Each apertured baffle-layer is at a respective distance zk from the pixel array and has a respective plurality of aperture stops Am forming an aperture-stop array. A center of each aperture stop Am is collinear with both a center of region Rm and an optical center of lens Lm. Each aperture-stop array has a pitch that approaches px as zk approaches zero and approaches lens pitch dx as zk approaches a distance zL between lens L0 and region R0. A width of each aperture stop Am has an upper limit that increases from px, when zk equals zero, to Wx when distance zk equals zL.

Abstract: An image sensor pixel array comprises a plurality of image pixel units to gather image information and a plurality of phase detection auto-focus (PDAF) pixel units to gather phase information. Each of the PDAF pixel units includes two of first image sensor pixels covered by two micro-lenses, respectively. Each of the image pixel units includes four of second image sensor pixels adjacent to each other, wherein each of the second image sensor pixels is covered by an individual micro-lens. A coating layer is disposed on the micro-lenses and forms a flattened surface across the whole image sensor pixel array. A PDAF micro-lens is formed on the coating layer to cover the first image sensor pixels.

Abstract: A pixel includes a semiconductor substrate, a photodiode region, a floating diffusion region, and a dielectric layer. The substrate has a top surface forming a trench lined by the dielectric layer, and having a trench depth relative to a planar region of the top surface. The photodiode region is in the substrate and includes a bottom photodiode section beneath the trench and a top photodiode section adjacent to the trench, adjoining the bottom photodiode section, and extending toward the planar region to a photodiode depth less than the trench depth. The floating diffusion region is adjacent to the trench and has a junction depth less than the trench depth. A top region of the dielectric layer is between the planar region and the junction depth. A bottom region of the dielectric layer is between the photodiode depth and the trench depth, and thicker than the top region.

Abstract: A pixel cell readout circuit includes an amplifier and a capacitor switch circuit that includes a first routing path coupled to an input of the amplifier. A second routing path includes switches coupled in series along the second routing path. A first end of the second routing path is coupled to a bitline. A second end of the second routing path is coupled to an output of the amplifier. Only one of the switches is turned off and a remainder of the switches are turned on. Capacitors are coupled in parallel between the first routing path and the second routing path. A first end of each of the capacitors is coupled to the first routing path. A second end of each of the capacitors is coupled to the second routing path. The switches are interleaved among the second ends of the capacitors along the second routing path.

Abstract: A shallow trench isolation (STI) structure and method of fabrication includes a two-step epitaxial growth process. A trench larger than the target STI structure is etched into a semiconductor substrate, a first layer of un-doped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth and a critical dimension, and a second layer of doped semiconductor material epitaxially grown on the first layer, said second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate.

Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.

Abstract: An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

Abstract: A structure light module comprises: a VCSEL substrate comprising a VCSEL array comprising a plurality of individual VCSELs; a first spacer disposed on the VCSEL substrate; a first wafer level lens comprising a glass substrate and at least a replicated lens on a first surface of the glass substrate disposed on the first spacer; a FOE disposed on the first wafer level lens; a second spacer disposes on the FOE; a second wafer level lens comprising a glass substrate and at least a replicated lens on a first surface of the glass substrate disposed on the second spacer; a third spacer disposed on the second wafer level lens; a DOE disposed on the third spacer, where a structure light is projected from the DOE on a target surface for 3D imaging.

Abstract: A pixel includes a semiconductor substrate, an upper surface thereof forming a trench having a trench depth relative to a planar region of the upper surface surrounding the trench, and in a plane perpendicular to the planar region; an upper width between the planar region and an upper depth that is less than the trench depth; and a lower width, between the upper depth and the trench depth, that is less than the upper width. A floating diffusion region adjacent to the trench extends away from the planar region to a junction depth exceeding the upper depth and is less than the trench depth. The photodiode region in the substrate includes a lower photodiode section beneath the trench and an upper photodiode section adjacent to the trench, beginning at a photodiode depth that is less than the trench depth, extending toward and adjoining the lower photodiode section.

Abstract: A method of routing electrical connections in a wafer-on-wafer structure comprises, bonding a metal bonding pad of a first wafer to a metal bonding pad of a second wafer; bonding first wafer to the second wafer with a material different from the metal bonding pads; forming metal interconnect structures connecting the metal bonding pad of the first wafer to a first device disposed within a first and second side of the first wafer; and forming metal interconnect structures connecting the metal bonding pad of the second wafer to a second and third devices disposed within the second wafer, to connect the first device to the second and third devices through the metal bonding pads, wherein the electrical connections of the devices between the first and second wafers do not have a through-via that passes completely through the first or the second wafer.

Abstract: A CMOS image sensor comprises an array of pixels. A column of the pixel array is coupled to a readout column. The readout column is couple to a readout circuitry (RC) that reads out image data from the pixel array. The RC comprises a sampling switch which is coupled to a 1-column successive approximation register (SAR) analog-to-digital converter (ADC). The 1-column SAR ADC comprises a differential comparator, a local SAR control, and a digital-to-analog converter (DAC). The sampling switch is coupled between a readout column and a non-inverting input of the differential comparator. An image readout method reads one pixel with two conversions through the RC. The RC is operated by the local SAR control to set the DAC based on comparator output, and upon which a reset digital value is obtained and stored. An overall reduced algorithm calculation is achieved herein.

Abstract: A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.

Abstract: An image sensor has an array of pixels, each pixel having an associated shutter transistor coupled to transfer a charge dependent on light exposure of the pixel onto an image storage capacitor, the image-storage capacitors being configured to be read into an analog to digital converter. The shutter transistors are P-type transistors in N-wells, the wells held at an analog power voltage to reduce sensitivity of pixels to dark current; in an alternative embodiment the shutter transistors are N-type transistors in P-wells, the wells held at an analog ground voltage.

Abstract: A flip-chip sample imaging device with self-aligning lid includes an image sensor chip, a fan-out substrate, and a lid. The image sensor chip includes (a) a pixel array sensitive to light incident on a first side of the image sensor chip and (b) first electrical contacts disposed on the first side and electrically connected to the pixel array. The fan-out substrate is disposed on the first side, is electrically connected to the first electrical contacts, forms an aperture over the pixel array to partly define a sample chamber over the pixel array, and forms a first surface facing away from the first side. The lid is disposed on the first surface of the fan-out substrate, facing away from the first side, to further define the chamber. The lid includes an inner portion protruding into the aperture to align the lid relative to the fan-out substrate.

Abstract: A LCOS display panel comprises a silicon substrate, a pixel structure on the silicon substrate, a first and a second PI (polyimide) layers, a LC (liquid crystal) layer between the first and the second PI layers, wherein the second PI layer is disposed on the pixel structure, and the LC layer is disposed on the second PI layer, a glass substrate, an ITO (indium tin oxide) layer, a dam sealing a perimeter of the LCOS display panel to enclose the LC layer within the dam, wherein the dam is disposed between the first and second PI layers, and holds the silicon substrate and the glass substrate together, and a UV (ultra violet) cut filter in an active area of the LCOS display panel, wherein the active area of the LCOS display panel includes the LC layer and the pixel structure.

Abstract: A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.