Abstract: A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.

Abstract: An inductor device includes a first coil, a second coil and a toroidal coil. The first coil is partially overlapped with the second coil in a vertical direction. The toroidal coil is disposed outside the first coil and the second coil. The first coil is interlaced with the second coil at a first side and a second side of the inductor device.

Abstract: A method and a system for accelerating verification procedure for an image file are provided. In the method, the system retrieves an image file from a first non-volatile memory, and calculates a hash value with respect to the image file. A combination of the hash value, a public key and a digital signature is compared with another hash value, public key and digital signature backup in a second non-volatile memory. A comparison result is generated for verifying the image file in the first non-volatile memory. After the image file is verified, the system can load the image file. Instead of the conventional technology that uses digital signature to verify the image file, the present method can effectively accelerate the verification procedure.

Abstract: A programmable gain amplifier includes a programmable resistor ladder deployed across Nmax junction nodes and controlled by Nmax?1 resistor control signals, where Nmax is an integer greater than one; a common-gate cascode amplifier multiplexer comprising Nmax common-gate cascode amplifiers configured to receive Nmax internal voltages at the Nmax junction nodes and output Nmax output currents in accordance with Nmax amplifier control signals, respectively, to an output node that is loaded with a load; and an AC (alternate current) coupling capacitor configured to couple an input node to the first junction node.

Abstract: The present disclosure discloses a signal relay apparatus having frequency locking mechanism that includes a receiving circuit, a frequency generation circuit, a frequency tracking circuit and a transmission circuit. The receiving circuit receives a receiving signal to retrieve data included therein according a corresponding receiving frequency signal. The frequency generation circuit receives a source clock signal and generates a target frequency signal according to a conversion parameter. The frequency tracking circuit calculates a frequency difference between the receiving frequency signal and the target frequency signal to adjust the conversion parameter accordingly. The transmission circuit generates a transmission signal that includes the data according to the target frequency signal.

Abstract: A circuit sleep method includes: writing all data stored in a memory unit into a current data-backup block and performing a check calculation on the data written into the current data-backup block to obtain a first verification value; powering down the circuit to make the circuit enter a sleep mode; restarting the circuit and determining whether the processing unit has written all the data stored in the memory unit into the current data-backup block before the circuit enters the sleep mode; performing the check calculation on the data stored in the current data-backup block to obtain a second verification value and comparing the first verification value with the second verification value; and writing back the data stored in the current data-backup block to the memory unit in a case that the first verification value and the second verification value are the same.

Abstract: An electronic device and a method of transmitting USB commands are provided. The method includes: (A) allocating a buffer area in a memory; (B) receiving a USB command; (C) retrieving control transfer information of the USB command; (D) storing the control transfer information in the buffer area; (E) repeating steps (B) to (D) until a condition for ending a control aggregation is met; (F) generating an aggregated USB command according to the content of the buffer area; and (G) transmitting the aggregated USB command.

Abstract: An artificial neural network and method are provided. The method includes receiving a set of input voltages; converting a respective input voltage in said set of input voltages into a respective set of local currents using a voltage-to-current conversion; multiplying said respective set of local currents by a respective set of binary signals to establish a respective set of conditionally inverted currents; summing said respective set of conditionally inverted currents into a respective local current; summing all respective local currents into a global current; and converting the global current into an output voltage using a load circuit.

Abstract: The present invention discloses an audio processing circuit, wherein when the audio processing circuit determines that a signal being processed is a small signal, an output stage uses a regulated supply voltage provided by a voltage regulator, and the output stage uses an open-loop structure to reduce noise of an output audio signal; and when the audio processing circuit determines that the signal being processed is a large signal, the output stage directly uses the supply voltage without using the regulated supply voltage, and the output stage uses a closed-loop structure to reduce the total harmonic distortion of the output audio signal. By using the present invention, the audio processing circuit can have a good performance indicator with a small chip area design.

Abstract: A receiver detection system includes a media access control (MAC) circuit, a common-mode voltage detector, and a receiver detector. The common-mode voltage detector is configured to detect whether a common-mode voltage satisfies a voltage condition, and to send a ready signal to the receiver detector after the common-mode voltage satisfies the voltage condition. The receiver detector is configured to start a detection process according to the ready signal and a detection start signal from the MAC circuit. In the detection process, the receiver detector sends out a detection signal for detecting whether a receiver exists, and then outputs a detection result to the MAC circuit, wherein the detection result indicates whether the receiver exists. The receiver detection system can prevent the receiver detector from starting the detection process before the common-mode voltage satisfies the voltage condition.

Abstract: A method for converting network packets and a circuit system are provided. The circuit system uses firmware therein to record tables for implementing packet conversion between two types of networks (IPv4 and IPv6). In the method, a process of mapping of address and port using encapsulation (MAP-E) or a process of mapping of address and port using translation (MAP-T) is determined according to IPv4 packets routing requirement to embody an uplink and a downlink packet conversion process. A content table stores an IPv6 packet header after the MAP-E or MAP-T process. A control table is referred to for controlling the fields to be updated when adding the IPv6 packet header. A forwarding mapping rule table is referred to for determining to convert a destination IP address of an uplink IPv6 packet, or both a source IP address and a destination IP address of a downlink IPv4 packet.

Abstract: The application discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device includes: a substrate; a circuit macro on the substrate; a plurality of metal layers over the substrate, wherein the plurality of metal layers include a first power mesh; and a plurality of power switch circuits on the substrate, wherein the power switch circuits selectively couple a power to the first power mesh according to a control signal, and the power switch circuits are arranged in sequence, wherein a control signal output terminal of each first power switch circuit is coupled to a control signal input terminal of a following first power switch circuit, so that the control signal passes through the first power switch circuits sequentially.

Abstract: The present invention provides an image processing method, wherein the image processing method includes the steps of: using a plurality of corner detection filters to perform corner detection on a specific pixel of image data to generate a plurality of detection results, respectively, wherein the plurality of corner detection filters correspond to a plurality of corners with different directions, respectively; determining which one of the plurality of corners with different directions the specific pixel belongs to according to the plurality of detection results; and according to a specific corner among the plurality of corners to which the specific pixel belongs, performing an image processing operation corresponding to the specific corner on the specific pixel to generate processed image data.

Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.

Abstract: An inspection method for an out-of-order execution processing circuit, includes determining that a refill request is not sent by a data cache unit of the out-of-order execution processing circuit before an exception commitment triggered by a permission check failure of the out-of-order execution processing circuit; and determining a key data is not read by a load-store unit of the out-of-order execution processing circuit and the key data is not utilized by a calculation unit of the out-of-order execution processing circuit before the exception commitment triggered by the permission check failure of the out-of-order execution processing circuit.

Abstract: A communication device includes: a wired communication circuit, a wireless communication circuit and a bit stream converter. The wired communication circuit is configured to exchange information with a host system via wired communication. The wireless communication circuit is configured to o exchange information with a wireless communication device via wireless communication. The bit stream converter is configured to selectively perform bit stream conversion on a bit stream between the communication device and the host system according to frequency band information corresponding to the wireless communication.

Abstract: The present invention provides a control method of a communication device, wherein the control method includes the steps of: controlling a wireless communication module of the communication device to use a first channel to communicate with an access point; detecting a plurality of channels to generate a plurality of first quality parameters, respectively, to generate a first channel detection result; receiving a second channel detection result from the access point, wherein the second channel detection result comprises a plurality of second quality parameters respectively generated by the access point detecting at least part of the plurality of channels; calculating a plurality of final quality parameters according to the first channel detection result and the second channel detection result; and determining whether to control the wireless communication module to switch from the first channel to a second channel according to the plurality of final quality parameters.

Abstract: A time-interleaved analog to digital converter includes coarse converter circuitries, a control logic circuit, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The coarse converter circuitries sequentially sample an input signal and perform coarse conversions to generate decision signals. The control logic circuit generates coarse digital codes according to the decision signals. The first and second transfer circuits respectively transfer first and second residue signals. The fine converter circuitry performs a fine conversion according to a corresponding first residue signal and a corresponding second residue signal to generate a fine digital code. A sampling interval for sampling the input signal and a coarse conversion interval for performing the coarse conversion are determined based on a fine conversion interval for performing the fine conversion.

Abstract: A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

Abstract: A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.