Abstract: A sensing device includes a sensed information transmitting circuit, a control information slave circuit and a mode switching circuit. The sensed information transmitting circuit converts sensed information into a transmission signal compliant with a signal format of a first transmission protocol. The control information slave circuit converts a received signal received from a signal transmission interface into control information according to a second transmission protocol, thereby to configure the sensing device. The mode switching circuit to activates one of the sensed information transmitting circuit and the control information slave circuit based on a signal on a clock channel of the signal transmission interface, a signal on a data channel of the signal transmission interface or a signal on a power rail of the sensing device, thereby to transmit or receive signals through the signal transmission interface.

Abstract: A LNA (low-noise amplifier) includes a matching network configured to provide a three-way coupling between an input node, a matched node, and a source node; a gate capacitor configured to provide AC (alternate current) coupling between the matched node and a gate node; a cascode amplifier configured to receive a gate voltage at the gate node and output an output voltage at an output node in accordance with a source degeneration at the source node; and a load network connected to the output node, wherein the matching network having a shunt inductor and a series inductor that are overlapped in layout to have a strong mutual coupling and a source degenerating inductor that is laid out in a close proximity to the shunt inductor to have a strong mutual coupling.

Abstract: A docking display has a multi-stream transmission (MST) port, an MST controller, a display panel, a control circuit, a hub, a first video output port, and a second video output port. The MST port is used for inputting at least one video stream. The MST controller is used for processing the at least one video stream. The control circuit is used for outputting a first video stream of the at least one video stream to the display panel to drive the display panel to display images according to the first video stream. When the at least one video stream has a plurality of video streams, the hub outputs a second video stream of the video streams from a first output port of the hub to the first video output port, or from a second output port of the hub through the MST controller to the second video output port.

Abstract: A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.

Abstract: The present invention provides a signal processing method, wherein the signal processing method includes the steps of: receiving a MST packet that complies with a DP specification; converting the MST packet into multiple SST packets; determining a number of valid data symbols in a transfer unit included in the multiple SST packets based on information of a horizontal blanking interval indicated by the MST packet or the multiple SST packets; and transmitting the multiple SST packets to a back-end device.

Abstract: A transmission method for increasing a transmission throughput of a communication device includes: receiving a wireless signal, wherein the wireless signal includes a received packet; determining whether the received packet is from an overlapping basic service set (OBSS), and determining a length of a duration of a transmission opportunity (TXOP) according to information carried by the received packet; in response to the received packet being from the OBSS, performing packet transmission in a spatial reuse manner within the duration of the TXOP; and performing the packet transmission in a general manner after the duration of the TXOP ends; wherein a transmission power utilized in the spatial reuse manner is different from a transmission power utilized in the general manner, and a plurality of packets are transmitted in the spatial reuse manner within the duration of the TXOP.

Abstract: A channel prediction method applied to channel change includes: selecting multiple candidate prediction channels from multiple channels in a channel database, and storing the multiple candidate prediction channels into a prediction database; comparing the multiple candidate prediction channels with a channel selected by a user to generate a comparison result; and selecting multiple prediction channels from the multiple candidate prediction channels in the prediction database according to the comparison result, and storing the multiple prediction channels into a channel buffer.

Abstract: The present invention provides a filter configured to receive an input signal to generate a filtered signal. The filter includes a first component, a first capacitor and a second component. The first component is coupled between the input signal and a first terminal. The first capacitor is coupled between the first terminal and a second terminal. For the second component, a first node of the second component is coupled to the second terminal, and a second node of the second component is used to output the filtered signal. The first component and the second component are inductive components.

Abstract: A signal transmitting system comprising: a first transmitting circuit, operating according to a first operation clock signal with a first phase; a second transmitting circuit, operating according to a second operation clock signal with a second phase, wherein the first phase and the second phase are different; and a multi-phase clock signal generating circuit, coupled to the first transmitting circuit and the second transmitting circuit, to generate the first operation clock signal and the second operation clock signal.

Abstract: A memory controller is arranged to access a memory device, and includes a receiving circuit. The receiving circuit is arranged to receive a data signal and a data strobe signal from the memory device, and includes a sampling circuit and a comparison circuit. The sampling circuit is arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal. The comparison circuit is arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result.

Abstract: The present invention provides a transceiver circuit, which includes a receiving circuit and a digital circuit, and the receiving circuit includes a first mixer, a second mixer, a bias voltage circuit, a complex filter and an ADC. In the operation of the transceiver circuit, the digital circuit controls the bias voltage circuit to sequentially switch the first bias voltage to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias values, wherein the plurality of first digital signals are used to calculate a plurality of first quality parameters respectively corresponding to the first bias values. The digital circuit controls the bias voltage circuit so that the first bias voltage has the first bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined according to the plurality of first quality parameters.

Abstract: An indicator circuit includes a power detection circuit and a codeword mapping circuit. The power detection circuit is coupled to a signal output terminal of a transmitter circuit, and is arranged to detect a power of an output signal to generate a detection result. The codeword mapping circuit is arranged to generate an indicator codeword according to the detection result, wherein the codeword mapping circuit converts the detection result according to a plurality of non-linear bases to correspondingly generate a plurality of converted detection results, and combines the plurality of converted detection results to generate the indicator codeword.

Abstract: A method for performing clock compensation in a communication device includes: determining a clock difference between a source operating clock and a target operating clock; performing clock compensation according to the clock difference, thereby obtaining a compensated time; and according to the compensated time, performing a clock synchronization process based on precision time protocol.

Abstract: A backlight control device adapted to control a plurality of backlight sources is provided. The backlight control device includes a timing control circuitry and a local-dimming control circuitry. The timing control circuitry is configured to generate a transmission packet according to a first customized content specification, where the transmission packet includes control information and brightness information. The timing control circuitry includes a differential circuit, where the differential circuit is configured to transmit the transmission packet according to a differential voltage level. The local-dimming control circuitry includes a receiving circuit electrically coupled to the differential circuit. The receiving circuit is configured to receive the transmission packet. The local-dimming control circuitry is configured to transmit a light source control signal according to the control information and the brightness information.

Abstract: A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Abstract: A method for data access control among multiple nodes and a data access system are provided. The data access system includes a data interconnect controller circuit that allocates resources of one or more slaves by one or more masters according to operating parameters of an interleaver, and includes an intelligent control module that collects use efficiency data of the one or more slaves and obtains a current setting of the data interconnect controller circuit via a monitor. The monitor calculates scores of use efficiency data. The scores and the setting are inputted to a neural network model. Parameters of the neural network model are adjusted according to the scores, and a new setting generated by the neural network model is applied to the interleaver of the data interconnect controller circuit, so that the data interconnect controller circuit performs access control among the multiple nodes with the new setting.

Abstract: A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

Abstract: A system, comprising: a plurality of first latches; a compressor circuit, coupled to the first latches, configured to compress an first signal having X bits from the first latches to a second signal having Y bits, wherein X and Y are positive integers and X is larger than Y; and at least one second latch, coupled to the compressor circuit, configured to receive the second signal to generate a scan output, wherein each of the first latches and the second latch forms a D flip flop. The system outputs the first signal but none of the scan output in a normal mode, and outputs the scan output but none of the first signal in a test mode.

Abstract: A transmission parameter decision method, used for a wireless transmission system with a plurality of user devices, includes (a) determining a plurality of characteristics corresponding to a current scene of the wireless transmission system at a first time point; and (b) determining a plurality of transmission parameters corresponding to each user device of the plurality of user devices at a second time point according to the plurality of characteristics; wherein the plurality of user devices perform wireless transmission using the corresponding plurality of transmission parameters at the second time point; wherein the second time point lags behind the first time point.

Abstract: The present invention provides a signal transmission method used in a host device. The signal transmission method comprises the steps of: receiving a plurality of commands, wherein the plurality of commands comprise at least two different types of commands; aggregating the plurality of commands to generate an aggregated command; and transmitting the aggregated command to an electronic device through a first interface circuit.