Abstract: A wireless communication method applied to a beamformer includes: receiving a plurality of reference information corresponding to a plurality of stations, respectively; calculating an evaluation value for each of the stations according to at least one reference information of the plurality of reference information; and comparing a plurality of evaluation values respectively corresponding to the plurality of stations, to select specific stations from the plurality of stations for performing beamforming.

Abstract: A memory access interface device that includes a clock generation circuit that generates reference clock signals according to a source clock signal and access signal transmission circuits are provided. Each of the access signal transmission circuits includes a first and a second clock frequency division circuits, a phase adjusting circuit and a duty cycle adjusting circuit. The first and the second clock frequency division circuits sequentially divide the frequency of one of the reference clock signals to generate a first and a second frequency divided clock signals respectively. The phase adjusting circuit adjusts the phase of an access signal according to the second frequency divided clock signal to generate a phase-adjusted access signal. The duty cycle adjusting circuit adjusts the duty cycle of the phase-adjusted access signal to be a half of the time period to generate an output access signal to access a memory device.

Abstract: A signal processing circuit includes: a printed circuit board (PCB) including a first surface layer, a second surface layer, a first reference layer, and a second reference layer, wherein the first and second surface layers are positioned on opposing side of the PCB while the first reference layer and the second reference layer are positioned between the first and second surface layers; a memory chip positioned on the first surface layer; a controller chip positioned on the second surface layer; a first set of signal lines arranged on the first surface layer and coupled with the memory chip, wherein all signal lines in the first set of signal lines does not cross each other; and a second set of signal lines arranged on the second surface layer and coupled with the controller chip, wherein all signal lines in the second set of signal lines does not cross each other.

Abstract: An audio device for reducing pop noise is adapted to compensate for a direct current (DC) offset of an audio source signal and output the audio source signal to an audio playing device. The audio device includes a linear operation circuit, an adder, a digital-to-analog circuit, and an amplification circuit. The digital-to-analog circuit is coupled between the adder and the amplification circuit. The linear operation circuit generates a DC offset value based on a linear equation, a temperature parameter, a slope parameter, and a constant. The adder is configured to process an input signal and the DC offset value to generate a calibration signal. The digital-to-analog circuit is configured to convert a calibration signal in a digital form to a calibration signal in an analog form. The amplification circuit is configured to process the calibration signal in the analog form to output the audio source signal.

Abstract: An image processing method and an image processing device are provided. The image processing method includes capturing a first image of a target irradiated by an infrared light; capturing a second image of the target not irradiated by the infrared light; performing noise suppression and signal enhancement on each of the first image and the second image to generate a first processed image and a second processed image; and processing the first processed image and the second image by a recognition device to recognize the target.

Abstract: A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

Abstract: The present invention provides a temporary memory processing method including: receiving a write command including a write data and a write address; determining whether a corresponding temporary address is in a missed state to generate a determined result; and determining whether to write the write data into a corresponding buffer address of a buffer memory according to the determined result.

Abstract: An OSD driving circuit is embedded in the display for controlling OSD operations of the display. The OSD driving circuit has a signal port and a microprocessor. The signal port is coupled to a signal channel for receiving an OSD opening command and for receiving an OSD execution command from a host via the signal channel. The OSD execution command is generated in response to operations of a cursor device of the host, and movement of a cursor displayed on a display panel of the display is controlled by the cursor device. The microprocessor is coupled to the signal port for driving the display panel to display an OSD menu according to the OSD opening command, and for executing OSD operations of the display according to the OSD execution command and coordinates of the cursor.

Abstract: This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.

Abstract: A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

Abstract: A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal.

Abstract: A multi-member Bluetooth device includes: a main Bluetooth circuit capable of directly communicating with a remote Bluetooth device through a Bluetooth transmission approach; and an auxiliary Bluetooth circuit capable of indirectly communicating with the remote Bluetooth device through the main Bluetooth circuit. After operating for a certain period, the main Bluetooth circuit transmits the main Bluetooth circuit's device identification data and multiple Bluetooth connection parameters between the main Bluetooth circuit and the remote Bluetooth device to the auxiliary Bluetooth circuit.

Abstract: A circuit and method are provided. The method couples a first bias signal to a first internal node via a first resistor, couples a second bias signal to a second internal node via a second resistor, couples the first internal node to a ground node via a N-type switch, couples the second internal node to a power supply node via a P-type switch. The method further couples the first internal node to the second internal node via a transmission gate, couples a terminal to the first internal node via a first capacitor, and couples the terminal to the second internal node via a second capacitor.

Abstract: The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder and the convolutional code decoding method of the present invention perform decoding using predictive information, and therefore can demodulate/decode signals more quickly. Earlier completion of demodulation/decoding of signals can terminate the operation earlier and thereby achieve the effect of power savings. The convolutional code decoder performs decoding according to received data and auxiliary data to obtain target data, and includes a first error detection data generation circuit, a channel coding circuit, a first selection circuit, a first Viterbi decoding circuit, a second error detection data generation circuit, a comparison circuit, a second selection circuit, and a second Viterbi decoding circuit.

Abstract: A circuit includes a first current source of a first type, a common-source gain device, a load, a second current source of a second type, a first common-mode network, and a second common-mode network. The first current source pulls a first bias current from a source node according to a first bias voltage. The common-source gain device receives an input voltage and outputs an output current to a drain node according to the first bias current. The load provides a termination to the drain node. The second current source outputs a second bias current to the drain node according to a second bias voltage. The first common-mode network outputs the first bias voltage according to a constant-gm reference current. The second common-mode network outputs the second bias voltage according to a difference between a mean voltage at the drain node and a scaled reference voltage.

Abstract: A circuit includes a first TSCP (tri-stage charge pump), a second TSCP, a third TSCP, a fourth TSCP, a fifth TSCP, and a load. The first TSCP receives a first phase and a third phase of a five-phase clock and outputs a first current to an output node. The second TSCP receives a second phase and a fourth phase of the five-phase clock and outputs a second current to the output node. The third TSCP receives a third phase and a fifth phase of the five-phase clock and outputs a third current to the output node. The fourth TSCP receives a fourth phase and the first phase of the five-phase clock and outputs a fourth current to the output node. The fifth TSCP receives a fifth phase and the second phase of the five-phase clock and outputs a fifth current to the output node. The load terminates the output node.

Abstract: A method for characterizing nonlinear distortion of a transmitter, an associated transmitter and a characterization circuit thereof are provided. The method includes: utilizing a transmitting chain circuit within the transmitter to generate an output signal according to a test signal; utilizing a loop back circuit within the transmitter to generate a loop back signal according to the output signal; calculating a plurality of distorted indices respectively corresponding to a plurality of test samples of the test signal according to a plurality of loop back samples of the loop back signal, wherein the plurality of test samples correspond to the plurality of loop back samples, respectively; dividing the plurality of distortion indices into multiple groups according to power of the plurality of test samples; calculating an average value of distortion indices within each group of the multiple groups; and characterizing the nonlinear distortion of the transmitter according to the average value.

Abstract: An ESD protection device includes a detection circuit and a clamping circuit. The detection circuit is configured to output a first control signal and a second control signal according to a first voltage and a second voltage that is different from the first voltage, in which if an ESD event occurs, the detection circuit is configured to perform an inverse operation according to the second voltage, in order to generate the first control signal and the second control signal. The clamping circuit is configured to be turned on according to the first control signal and the second control signal, in order to provide a discharging path for a current associated with the ESD event.

Abstract: This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.

Abstract: The present invention discloses a wireless transceiver capable of offsetting internal signal leakage. The wireless transceiver includes a transmission circuit, a reception circuit and a calibration circuit. The calibration circuit generates a first estimation signal according to the difference between a test signal and a reception digital signal passing through a standard path, generates a second estimation signal according to the difference between the test signal and a reception digital signal passing through a leakage path, and then determines N coefficient(s) of a calibration filter according to the difference between the first estimation signal and the second estimation signal. Therefore, the calibration circuit including the calibration filter can output a calibration signal to the reception circuit to offset at least a part of the signal leakage from the transmission circuit to the reception circuit.