Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Abstract: In a serial communication circuit, a data extracting section extracts reception data based on a reception clock signal with maximum speed. A pattern determining section compares a reception bit pattern of the reception data corresponding to a characteristic pattern and each of a plurality of detection bit patterns for the characteristic pattern, and indicates when the reception bit pattern matches one of the detection bit patterns. A periodicity determining section determines a period when the reception bit pattern matches the detection bit pattern, based on the pattern match indication, detects that the detection bit pattern emerges continuously in a stream of the reception data every the period, and determines a generation difference between transmission and reception speeds based on the detection bit pattern. A transmission rate setting section determines the transmission speed of a connected device transmitting the reception data based on the generation difference and maximum speed.

Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector. Whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.

Abstract: The present invention makes it possible to increase the reliability of a semiconductor device. A manufacturing method of a semiconductor device according to the present invention includes a step of removing a patterned resist film and the step of removing a patterned resist film includes the steps of: (A) introducing at least a gas containing oxygen into a processing room; (B) starting electric discharge for transforming the gas containing oxygen into plasma; and (C) introducing a water vapor or an alcohol vapor into the processing room. On this occasion, the step (C) is applied either simultaneously with or after the step (B).

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: To improve a quality of a combined signal obtained by maximum ratio combining performed when a transmission signal of OFDM system is diversity-received with a small computation amount or a small circuit size. In a receiving apparatus, a combining unit corrects, when combining a sub-carrier signal of each branch obtained by performing Fourier transform on a reception signal of each branch at a maximum ratio for each sub-carrier, a weighting coefficient of each branch according to a magnitude relation of an intensity of the reception signal of each branch before Fourier transform. Specifically, the combining unit corrects the weighting coefficient of each branch so as to weaken an influence of a transmission path response estimated for a sub-carrier signal of the branch in branches with smaller reception signal intensities.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.

Abstract: The present invention provides a magnetoresistive effect element which performs writing by a novel method. In a state in which a current does not flow in a magnetization free layer MFR, the magnetization free layer MFR has a magnetic wall MW1 on the side of a magnetization fixed layer MFX1. A magnetic wall MW2 is moved to the magnetic wall MW1 side by causing current to flow from the formed side of the magnetic wall MW1. Thus, an electrical resistance RMTJ between a reference layer REF and the magnetization free layer MFR changes from a low state to a high state.

Abstract: When plural diffusion layers are shared in order to save an area of a semiconductor integrated circuit, parasitic capacities of wirings coupled to those diffusion layers are changed. Nonetheless, a semiconductor layout balancing capacitive loads of paired wirings coupled to the diffusion layers with each other is provided. The diffusion layers coupled to the respective paired wirings are alternately arranged or staggered to balance the respective capacitive loads of the paired wirings with each other.

Abstract: A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and a fourth point on the periphery of the main surface between the third side and the second side, a first semiconductor chip disposed over the main surface of the substrate, and a second semiconductor chip disposed over the main surface of the substrate.

Abstract: A data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections.

Abstract: It is an object of the present invention to provide a technology that a microcomputer is capable of detecting the states of a large number of switches with a small number of ports. In a microcomputer system according to the present invention, any one of (2N?1) kinds of the combination patterns with respect to the combination of N input ports (IP1 to IP4) of a microcomputer (1) is allocated to each of M push-down switches (SW12, SW13, SW14, SW23, SW24, and SW34) with the different combination from each push-down switch. Each push-down switch inverts the input levels of the input ports in the combination pattern allocated thereto when pushed down. The microcomputer (1) detects the state of each push-down switch on the basis of the input levels of the N input ports.

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract: Parts of electronic components are not exposed to temperature deviating from an appropriate operation temperature range when an electric characteristic test of a semiconductor module having an interposer substrate over which plural kinds of electronic components are mounted is carried out. A heat sink for an electronic component is incorporated in a lid of a test socket used for an electric characteristic test of an MCM. A heat dissipation sheet is attached to part of the bottom face of the heat sink and an adiabatic sheet is attached to another part. The heat dissipation sheet has thermal conductivity larger than the adiabatic sheet and transfers heat generated from an electronic component of a high heat value to the heat sink during operation. The adiabatic sheet inhibits the heat generated from an electronic component of high heat value from being transferred to another electronic component through the heat sink.

Abstract: A semiconductor memory device has a cover film (5), between a memory cell (gate electrode 4, and source and drain regions 2a and 2b) and an interlayer insulating film (6), the cover film covering the memory cell, wherein the cover film (5) has a hydrogen storage film (5a) that is a coating film on a surface of a silicon nitride film (5b), and in addition, has a hydrogen storage film (5c) on a bottom surface of the silicon nitride film (5b). The hydrogen storage films (5a and 5b) are silicon nitride oxide films that include Si2N2O. By suppressing diffusion of hydrogen atoms to a memory cell from an interlayer insulating film, reliability of operation of the memory cell is improved.