Abstract: Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed.

Abstract: A trench portion (trench or groove) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract: An improvement is achieved in the performance of a semiconductor device. A method of manufacturing the semiconductor device includes an exposure step of subjecting a resist film formed over a substrate to pattern exposure using EUV light reflected by the top surface of an EUV mask which is a reflection-type mask. In the exposure step, the EUV mask is held with the cleaned back surface thereof being in contact with a mask stage. In the EUV mask, the water repellency of the side surface thereof is higher than the water repellency of the top surface thereof. After the exposure step, the resist film subjected to the pattern exposure is developed to form a resist pattern.

Abstract: The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

Abstract: A semiconductor wafer with modified regions formed in the substrate is provided. A modified region is formed apart from the side of a wafer and a pad is formed over an insulating film, which is formed over the main surface of the substrate of the wafer. Further, the modified region is formed closer to the side surface of the substrate than the pad. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.

Abstract: A semiconductor device is provided in which reliability of the semiconductor device is improved by improving an EM characteristic, a TDDB characteristic, and a withstand voltage characteristic of the semiconductor device. An average diameter of first vacancies in a lower insulating layer which configures an interlayer insulating film of a porous low-k film for embedding a wiring therein, is made smaller than an average diameter of second vacancies in an upper insulating layer, and thereby an elastic modulus is increased in the lower insulating layer. Further, a side wall insulating layer which is a dense layer including the first vacancies having an average diameter smaller than the second vacancies is formed on the surface of the interlayer insulating film exposed on a side wall of a wiring trench.

Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract: A delta-sigma modulator is configured to feedback an output signal of a quantizer to an input of an integrator, and also feedback to the input of the integrator a differentiated error signal representing derivative of quantization error caused by the quantizer.

Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating fAh and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.

Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.

Abstract: A power line carrier transmission apparatus according to an aspect of the present invention is a power line carrier transmission apparatus that transmits a transmission symbol via a transmission path. The transmission apparatus includes a frequency/time interleave unit that interleaves the transmission symbol, an OFDM modulation unit that OFDM-modulates the interleaved transmission symbol, a time-domain repeated transmission unit that repeatedly transmits the transmission symbol, which is modulated by the OFDM modulation unit, M times (M is an integer larger than 1) in a time domain.

Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N?-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N?-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N?-type drift region. The N?-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N?-type drift region.

Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: In this flash memory, after first and second nodes are precharged to a power supply voltage, a sense amplifier is activated, and signals appearing at the first and second nodes are held in a register. With output signals of the register, a transistor is rendered conductive, so that a constant current source for offset compensation is connected to the first or second node. Accordingly, the offset voltage of the sense amplifier can be compensated for with a simple configuration.