Abstract: A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.

Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.

Abstract: The disclosed invention provides a semiconductor device that enables early discovery of a sign of aged deterioration that occurs locally. An LSI has a plurality of modules and a delay monitor cluster including a plurality of delay monitors. Each delay monitor includes a ring oscillator having a plurality of gate elements. Each delay monitor measures a delay time of the gate elements. A CPU #0 determines if a module proximate to a delay monitor suffers from aged deterioration, based on the delay time measured by the delay monitor.

Abstract: network signal value is received (610) from one or more access points in response to a request to employ carrier aggregation. An additional maximum power reduction of a plurality of uplink and downlink signals among two or more radio bands is selectively produced (620) based upon the network signal value and a plurality of dynamic additional maximum power reduction parameters.

Abstract: The optical disc device has a circuit which forms a focus error signal for focus servo control based on reflection light from an optical disc exposed to laser light. Also, the device has a data processing unit which can control by feedback a position to which an objective lens is moved by a focusing actuator based on a focus error signal. In label printing, the data processing unit controls, by feedforward, a position to which the objective lens is moved by the focusing actuator based on control data for label printing. The operation resolution of the focusing actuator in feedforward control is made higher than that in feedback control. Thus, an intended position control accuracy is achieved in feedforward control. For instance, in feedforward control, the gain of the driver circuit for the focusing actuator is switched to a smaller one in comparison to that in feedback control.

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract: The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar.

Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Abstract: A first control unit (172), which controls the timing at which a first image pickup unit (110) starts exposure, obtains a second difference (?t2) by subtracting a first difference (?t1) from an exposure-output time (AA) of the first image pickup unit (110), and outputs a first control signal (CTR1) for delaying the timing at which the first image pickup unit (110) starts an exposure, by the second difference (?t2). The exposure-output time is a time lag between when the image pickup unit starts an exposure and when output of an image signal obtained by the exposure is started. The first difference (?t1) is a difference between a timing at which the first image pickup unit (110) started outputting a predetermined image signal and a timing at which a second image pickup unit (150) started an exposure for obtaining an image signal that the second image pickup unit (150) outputted immediately after the first image pickup unit (110) started outputting the predetermined image signal.

Abstract: Each stitch part of a plurality of leads of a package has a first region having the most outer surface on which Ag plating is applied and a second region having the most outer surface on which Ni plating is applied. Further, the second region is arranged on a die pad side, and the first region is arranged on a periphery side of a sealer. Therefore, in each stitch part, types of plating applied on the most outer surfaces of the first region and the second region can be differentiated from each other, a thick Al wire can be connected to the second region of the second lead, and a thin Au wire can be connected to the first region of the first lead. As a result, usage of only Au plating can be avoided, so that the cost of the package is reduced.

Abstract: A display driver circuit includes an input terminal configured to receive an input signal, an output terminal configured to output an output signal, a slew rate control circuit configured to input the input signal and the output signal, and output a pair of differential input signals based on a voltage difference between the input signal and the output signal; a differential input circuit configured to input the pair of the differential input signals and output a pair of differential output signals, wherein the differential input circuit includes a first current mirror circuit and a second current mirror circuit, and an output circuit configured to input the pair of the differential output signals and output the output signal to the output terminal.

Abstract: Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs.

Abstract: A content addressable memory includes a memory array having a plurality of match lines extending in a first direction, a plurality of search lines extending in a second direction perpendicular to the first direction, and a plurality of memory cells, each disposed at points where the match lines and the search lines intersect. The content addressable memory also includes a plurality of search line drivers, each of the search line drivers being provided to drive the search lines based on search data; a search control circuit generating a search line enable signal, and including a first and a second transistor, the first transistor) for output the search line enable signal and the second transistor for receiving the search line enable signal; and a control signal wiring coupled to the search control circuit and transmitting the search line enable signal to each of the search line drivers.

Abstract: A semiconductor device includes an adjustment data generation unit receiving at least a part of adjustment values of color attributes of each of n-axis vertices (n is an integer not less than 3), the n axes serving as an adjustment axis in a RGB color space. The adjustment data generation unit calculates the degree of influence which indicates the following index of each of the n-axis vertices based on the distance between each of the n-axis vertices and a target point which is an arbitrary lattice point in the RGB color space. The adjustment data generation unit calculates adjusted coordinates of the target point in the RGB color space based on shifting of each of the n-axis vertices in the RGB color space according to the adjustment value and the degree of influence. The image adjustment unit performs color adjustment of inputted image data.

Abstract: A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential.

Abstract: A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor.

Abstract: The present invention realized miniaturization of a power supply device using a multiphase system. The power supply device includes, for example, a common control unit, a plurality of PWM-equipped drive units, and a plurality of inductors. The common control unit outputs clock signals respectively different in phase to the PWM-equipped drive units. The clock signals are controllable in voltage state individually respectively. For example, the clock signal can be brought to a high impedance state. In this case, the PWM-equipped drive unit detects this high impedance state and stops its own operation. It is thus possible to set the number of phases in multiphase arbitrarily without using another enable signal or the like.