Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract: A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.

Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.

Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

Abstract: The semiconductor device of the present invention includes: a MOSFET having a gate electrode formed via a gate insulating film over a semiconductor layer and source and drain regions formed in the semiconductor layer on both sides of the gate electrode; and a diode. The diode has an n+-type semiconductor region, a p-type semiconductor region and a p+-type semiconductor region. Then, the gate electrode is connected to the n+-type semiconductor region via an n-type semiconductor region formed so as to be connected to the n+-type semiconductor region. Also, the p+-type semiconductor region is connected to a semiconductor layer below the gate electrode. In this way, by providing the diode between the back gate and gate electrode of the MOSFET, breakage of the gate insulating film can be prevented.

Abstract: The application relates to a mobile terminal radio stack for D2D single channel (308) and a cellular uplink single channel (324). A D2D connection is a direct connection formed between a first mobile terminal and a second mobile terminal over the cellular radio spectrum. The D2D connection is a local communication link and is generally enabled for use over short distances. Because the D2D connection could be lost quite rapidly, handover (e.g. bearer establishment) of the D2D communications to traditional cellular communications e.g. Evolved Universal Mobile Telecommunications System Terrestrial Radio Access Network (E-UTRAN)) may not occur in time to synchronize the multiple mobile terminals. As a result, multiple protocol data units between the mobile terminals may be lost.

Abstract: Provided is a semiconductor device having improved performance and an improved manufacturing yield. Over photodiodes formed in a semiconductor substrate, a plurality of first to third embedded insulating films are stacked to form a waveguide for light incident on each of the photodiodes. The first embedded insulating film is formed simultaneously with plugs when the plugs are formed. The second embedded insulating film is formed simultaneously with first wires when the first wires are formed. The third embedded insulating film is formed simultaneously with second wires when the second wires are formed.

Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.

Abstract: Guide information according to a hierarchy of a given character string is sequentially acquired in response to an input of character strings for describing a source program, and only the guide information is displayed depending on an input status of the character string. Characters input from an input device for software description are coupled with each other to create an input character string. The created input character string is divided for each of the number of hierarchies on the basis of the number of hierarchies sectioned by a member access operator indicative of an access to a member of a structure or a class to acquire hierarchical character strings and hierarchy numbers thereof. The corresponding hierarchy of the hierarchical database is searched with the hierarchical character string as a search key for each of the acquired hierarchy numbers.

Abstract: The present invention realizes stabler output voltage variable control in a power supply unit. A power supply unit capable of changing dynamic output voltage has: a first regulator for dropping down voltage, by a switching method and outputting the resultant voltage to a first node; and a second regulator for dropping down the input voltage by a voltage drop and outputting the resultant voltage to the first node. In the case where a target voltage instructed by first information is larger than a predetermined threshold voltage, the power supply unit controls so that the voltage of the first node becomes the target voltage and stops supply of voltage from the second regulator. In the case where the target voltage is smaller than the predetermined threshold voltage, the power supply unit controls the second regulator so that the voltage of the first node becomes the target voltage and stops output of voltage from the first regulator.

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.

Abstract: A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), a gate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract: In accordance with an example embodiment of the present invention, a method is disclosed that comprises obtaining a new signal quality threshold based on a base signal quality threshold and a context-sensitive buffer margin and setting a current triggering threshold to the obtained new signal quality threshold if the current triggering threshold is smaller than the obtained new signal quality threshold.

Abstract: A rotation number measurement device includes a detection circuit for generating a signal that differs depending on whether a first area is near or a second area is near by rotation of a rotating plate, a determination circuit which receives the signal of the detection circuit and a reference value and determines the signal based on the reference value, a counting circuit for obtaining a count indicating that a determination of the determination circuit with a first period during a first duration is a signal corresponding to the first area, and a reference circuit for generating the reference value so that a ratio between a count indicating that a determination of the determination circuit with the first period during the first duration is a signal corresponding to the second area and the count of the counting circuit becomes equal to a ratio between the second area and the first area.

Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.

Abstract: A solid-state image pickup device 1 includes a semiconductor substrate 10, light receiving unit 14 and light shielding film 20. The solid-state image pickup device 1 is back surface incident type and photoelectrically converts light indent on the back surface S2 of the semiconductor substrate 10 from an object into electrical charges and receives electrical charges produced by photoelectric conversion at the light receiving unit 14 to image the object. The light receiving unit 14 forms a PN junction diode with the semiconductor substrate 10. The light shielding film 20 is provided over a front surface S1 of the semiconductor substrate 10 so as to cover the light receiving unit 14. The light shielding film 20 serves to shield light incident on the front surface S1 from the outside of the solid-state image pickup device 1.