Abstract: A level shift circuit includes a first pair of transistors of the first conductive type (M1, M4) with sources coupled to a pair of input nodes (in, inB) and gates coupled to the first power supply (GND) in common; a second pair of transistors of the second conductive type (M2, M5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (M3, M6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (V2) in common; and a pair of capacitative elements (C1, C2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.

Abstract: A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

Abstract: In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage.

Abstract: An apparatus and method in which a User Equipment (UE) can register with a wireless network without requiring a packet data connection to be established. Embodiments are described in which a UE can indicate to a Mobility Management Entity that a packet data connection is not required to be established immediately. This can free resources when the UE knows that it will not need to transmit or receive data for some time, which is often the case for UE using Machine to Machine communication. In other embodiments, the MME can delay the establishment of a data connection for a UE if there are temporarily not enough resources to support it. In one embodiment, an apparatus for configuring a user equipment for transmission of data over a wireless network is provided.

Abstract: In a related transmitting circuit employing electromagnetic induction that is used in a communication system, there is a problem in that, because only one inductor is used in the transmitting circuit, it is impossible to perform communication at a data rate higher than the self-resonant frequency of the inductor. A transmitting circuit according to an embodiment of the present invention is a transmitting circuit that drives an inductor to transmit data to a semiconductor chip insulated from a semiconductor chip on which the transmitting circuit is mounted, and includes a driving circuit that receives outgoing data transmitted at a data rate higher than the self-resonant frequency of the inductor and outputs an outgoing signal that drives the inductor at the data rate of the outgoing data.

Abstract: A semiconductor device in which unwanted change in the secondary data which must be reliable is suppressed and the need for a considerable increase in the capacity of a memory unit can be avoided. Also it ensures efficient data processing by asymmetric access to the memory unit. It includes a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the memories. A plurality of buses is coupled to the access nodes and a plurality of data processing modules can asymmetrically access the memory unit through the buses. The first memory stores primary data before data processing by the data processing modules, and the second memory stores secondary data after data processing by the data processing modules.

Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N?-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N?-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N?-type drift region. The N?-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N?-type drift region.

Abstract: Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an external section and a plurality of processor elements in an SIMD processor, so that one rectangular region corresponds to one processor element. In the SIMD processor, an address storage unit in a memory controller is capable of setting N number of addresses Ai (i=1 through N) in an external memory by utilizing a control processor. A parameter storage unit is capable of setting a first parameter OSV, a second parameter W, and a third parameter L by utilizing a control processor. A data transfer unit executes the transfer of data between an external memory, and the buffers in N number of processor elements contained in the applicable SIMD processor, based on the contents of the address storage unit and the parameter storage unit.

Abstract: A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region.

Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.

Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Abstract: To variably change the filter characteristic of a decimation filter in accordance with a sampling rate. A decimation filter 13 in a semiconductor device 1 sequentially inputs a signal sampled at a predetermined sampling rate fos, and calculates, for each input signal that is input within a predetermined period (a period for M+2N), a filter coefficient Cj for performing predetermined filtering processing in response to a trigger signal TR continuously applied, and furthermore sequentially multiplies the input signal by the calculated filter coefficient, accumulates a multiplication value within the predetermined period, and sequentially outputs the result. The predetermined period is made variable in accordance with a time interval at which the trigger signal is applied.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: A semiconductor device, includes a first substrate having a main surface and a rear surface opposing to the main surface, a first circuit including a plurality of transistors formed over the main surface, a first insulating film formed over the main surface to cover the first circuit, a first inductor formed in the first insulating film over the main surface, the first inductor being electrically connected to the first circuit; and a bonding pad formed over the main surface, the bonding pad being located at a first area, the first inductor being located at a second area, the first area being different from the second area in a plan view, and a second substrate having a main surface, a rear surface opposing to the main surface and a second inductor formed over the main surface.

Abstract: To determine the accuracy of an AD converter more simply than in the related art, a semiconductor device includes a successive approximation AD converter. The AD converter includes one or a plurality of testing capacitors used in a test mode, separately from a C-DAC used for AD conversion in a normal mode. In the test mode, the accuracy of a capacitor under test among a plurality of capacitors configuring the C-DAC is determined by comparing a potential occurring in the capacitor under test and a potential occurring in the testing capacitors.

Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization.