Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract: A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.

Abstract: The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode.

Abstract: Disclosed is a semiconductor device including a semiconductor chip and a semiconductor package. The semiconductor package includes an antenna formed of a lead frame, a first wire that connects the antenna and a first electrode pad of the semiconductor chip, and a second wire that connects the antenna and a second electrode pad of the semiconductor chip. The semiconductor chip is disposed in one of four regions in the semiconductor package sectioned by line segments connecting midpoints of two pairs of opposing sides of the semiconductor package. A centroid of the semiconductor chip is positioned outside a closed curve composed of a straight line segment connecting a first connection point where the antenna and the first wire are connected and a second connection point where the antenna and the second wire are connected, and a line connecting the first and second connection points along the antenna.

Abstract: There is provided, for example, an apparatus, which is caused to select a transmission power configuration for a communication with at least one user terminal taking place on component carriers of a carrier aggregation configuration within a shared band, wherein the selection is between a low transmission power configuration applying a transmission power below a predetermined power threshold without a listen-before-talk approach and a high transmission power configuration applying a transmission power of at least the predetermined power threshold; and upon detecting that the selected transmission power configuration needs to be informed, cause an indication of the selected transmission power configuration to the at least one user terminal and at least one secondary cell.

Abstract: The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.

Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.

Abstract: The present invention properly starts up various types of motors under operating conditions where motor operations are performed in a wide range of temperature and power supply voltage. Output drive controllers supply PWM drive output signals to the output pre-driver in such a manner as to minimize the error between a current instruction signal and a current detection digital signal. In response to a detected induced voltage generated from a voltage detector upon startup of a motor, an initial acceleration controller supplies initial acceleration output signals specifying a conducting phase for initial acceleration of the motor to the output drive controllers. The initial acceleration controller, the output drive controllers, and an output driver make a conducting phase change and perform a PWM drive to provide the initial acceleration of the motor in response to the detected induced voltage and to an error upon startup of the motor.

Abstract: A semiconductor device according to the present invention includes a first address generation unit that includes a first register group and generates a table address by a cyclically repeating first pattern using a value stored to the first register group, a second address generation unit that includes a second register group and generates an access address by a cyclically repeating second pattern using a value stored to the second register group and parameter information determined by the table address, and a control unit that outputs setting information to be supplied to the first register group and the second register group. Further, the semiconductor device performs at least one of a read process and a write process of data from and to a data memory using the access address.

Abstract: Embodiments of the invention provide a method of configuring a transceiver to transmit and receive signals at a plurality of frequencies including at least a first transmitted signal modulated at a first transmission frequency, a first received signal modulated at a first reception frequency, and a second transmitted signal modulated at a second transmission frequency, the method comprising: responsive to detecting desensitisation at the first reception frequency, configuring the transceiver so that at least two of the first received signal, the first transmitted signal and the second transmitted signal are transceived in a partial time division duplex, frequency division duplex mode. Embodiments also include apparatus comprising a transceiver, the apparatus being suitably configured to perform the method.

Abstract: Methods for devices, devices and computer program products for devices relate to a communication module, arranged for packet based communication, and including a receiving module. The receiving module is arranged to receive a control message, wherein the control message includes a plurality of acknowledgement information items, wherein each of the plurality of acknowledgement information items are located in a preset portion of the control message, respectively. The device further includes a determination module, arranged to determine whether the received control message is intended for the device, a selection module, arranged to select, responsive to an affirmative determination result, at least one of the plurality of acknowledgement information items based on the preset portions, and an obtaining module, arranged to obtain control data contained in the selected at least one of the plurality of acknowledgement information items.

Abstract: An apparatus includes: an offset adjustment unit supplying an offset correction signal corresponding to a frequency switching to an adder unit receiving output from a mixer; a timing adjustment unit adjusting the timing of a frequency switching signal supplied to a local oscillator and the timing of an offset correction amount switching signal supplied to the offset adjustment unit for changing an offset amount in correspondence with the frequency switching in the local oscillator; a noise amount measurement and calculation unit receiving a signal obtained by amplifying and filtering the signal from the adder unit, to measure a noise amount of the signal and generates a timing determination signal based on the noise amount; and a control unit controlling frequency switching signal timing and the offset correction amount switching signal supplied to the timing adjustment unit, based on the timing determination signal from the noise amount measurement and calculation unit.

Abstract: A method is provided that includes allocating a first subset of resource elements (REs) of a physical resource block (PRB) to a mobile terminal and associating one or more first demodulation reference symbols (DM-RS) ports therewith. The first subset of REs and the one or more first DM-RS ports have common interference characteristics, thereby providing for enhanced interference suppression. The method also includes causing transmission of the PRB for reception by the mobile terminal. Corresponding apparatus and computer program products are also provided.

Abstract: A level shift circuit includes a first pair of transistors of the first conductive type (M1, M4) with sources coupled to a pair of input nodes (in, inB) and gates coupled to the first power supply (GND) in common; a second pair of transistors of the second conductive type (M2, M5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (M3, M6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (V2) in common; and a pair of capacitative elements (C1, C2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: In a wireless communications network, a user equipment is capable of operating in a first mode in which uplink signals are transmitted using a single antenna and in at least a second mode in which uplink signals are transmitted using two or more antennas. It is determined at the user equipment whether to request activation of the first or second mode and a first message is sent to a network node requesting activation of the first or second mode together with Medium Access Control (MAC) Scheduling Information (SI). Alternatively, the user equipment sends, to the network node, an indication of a threshold for use in determining whether to activate the first or second mode together with user equipment capability information. A second message is received at the user equipment from the network node indicating whether the first or second mode should be activated.

Abstract: A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.