Abstract: A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer.

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.

Abstract: The present invention improves the transmission power characteristics of a wireless communication device or reduces the resources required for improving the transmission power characteristics. The wireless communication device includes, for example, a bias detection circuit, an error amplifier, and a correction circuit. The bias detection circuit detects a bias that is supplied to a high-frequency power amplifier. The error amplifier amplifies the error between the detected bias and a predetermined reference voltage. The correction circuit searches for a bit correction value that minimizes the error detected in the error amplifier. During a normal operation, a digital-to-analog conversion circuit receives a bias instruction code from a baseband unit and outputs a bias setup voltage, which is obtained when the bit correction value is reflected in the bias instruction code. A bias corresponding to the bias setup voltage is then supplied to the high-frequency power amplifier.

Abstract: There are provided measures for cell search and synchronization. Such measures may exemplarily comprise acquiring an observation signal for a carrier signal on a carrier which is under consideration for synchronization with a desired cellular system, calculating a power measure of the observation signal, which indicates a received power of said carrier signal, calculating a non-circularity measure of the observation signal, which indicates a non-circularity of said carrier signal, and calculating a ranking measure, which indicates an applicability of said carrier for synchronization with the desired cellular system, based on the calculated power measure and the calculated non-circularity measure.

Abstract: Operation parallelism of a data processor is enhanced by floating-point inner product execution units compatible with single instruction multiple data (SIMD). An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining efficiency of floating-point length-4 vector inner product execution units is implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically.

Abstract: The present invention proposes an apparatus which comprises a communication module configured for communication in a carrier aggregation mode aggregating a primary and at least one secondary carrier, a measurement module, and a control module, configured to retrieve measurement information pertaining to a measurement to be conducted of at least one secondary carrier associated to the primary carrier in the carrier aggregation mode, and instruct the measurement module to conduct a measurement of the at least one secondary carrier based on the measurement information, determine, based on a measurement result, an extent to which the measured secondary carrier is usable for transmission. Also, a corresponding method and computer program product is proposed.

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract: Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.

Abstract: A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator.

Abstract: The present invention reduces the size of a power detection circuit. An RF power amplifier includes an RF amplifier circuit and a power detection circuit. The RF amplifier circuit subjects an RF input signal having a predetermined frequency band to power amplification and generates an RF amplifier output signal. The input terminal of the power detection circuit is coupled to the output of the RF amplifier circuit. The power detection circuit detects a harmonic component having a harmonic frequency that is a whole number multiple of the frequency of a fundamental wave component of the RF amplifier output signal, and generates at an output terminal a detected signal indicative of the signal level of the fundamental wave component of the RF amplifier output signal. The power detection circuit includes an input circuit, which detects the harmonic component, and an output circuit, which generates the detected signal at the output.

Abstract: An allowable current amount of a ballast resistance is increased without increasing the width of the ballast resistance. At least one of resistances included in a ballast resistance has a first resistance and a second resistance. The first resistance extends in a first direction (X direction in FIG. 1) in which current flows in a protection element. The second resistance element is coupled in parallel to the first resistance element and extends in the first direction. The second resistance element and the first resistance element are located on the same straight line.

Abstract: The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request.

Abstract: A method, apparatus and computer program product are provided in order to enable operation of both cellular and WLAN on a shared unlicensed band. In this regard, a method is provided that includes causing a primary transmission mode period of operation, a secondary transmission mode period of operation, and an idle mode period of operation on an unlicensed frequency band to be transmitted to a mobile terminal. The method further includes receiving an interfered ratio report from the mobile terminal. The method also includes causing the mobile terminal to be classified as at least one of a primary user or a secondary user based on the interfered ratio report. The method also includes causing the classification to be transmitted to the mobile terminal.

Abstract: A current supply unit supplies a current between first and second current output terminals. A voltage measurement unit measures a voltage input to first and second voltage input terminals. A control circuit causes a first switch unit to connect the first current output terminal to a first terminal of a reference resistor and to connect the second current output terminal to a second terminal of the reference resistor, causes a second switch unit to connect the first voltage input terminal to the first terminal of the reference resistor and to connect the second voltage input terminal to the second terminal of the reference resistor, and causes a voltage measurement unit to measure a voltage between the first and second voltage input terminals, thereby performing self-diagnosis of a path through which a current flows.

Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Abstract: Various methods for enabling D2D connections to exchange P2P data so as to reduce traffic on a network. One example method may comprise constructing a local topology of one or more mobile terminals. The method of this embodiment may also include determining that a mobile terminal of the one or more mobile terminals has initiated a peer to peer session. The method of this embodiment may also include determining, based on the local topology, one or more mobile terminals to act as one or more seeder devices for the peer to peer session. The method of this embodiment may also include causing the local topology to be transmitted to the mobile terminal that has initiated the peer to peer session. In some example embodiments, the mobile terminal is configured to use the local topology to initiate a device to device connection for the peer to peer session.

Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.

Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.