Abstract: This invention allows for stable operation of a circuit to which an output voltage is supplied. The invention resides in a semiconductor device comprising a VREF1 regulator to which a reference voltage Vref1 relative to a first potential is input; and an output circuit which generates an output voltage Vint that is proportional to a voltage on its input terminal relative to a second potential. The VREF1 regulator comprises a constant current source which generates a constant current having a current value that is proportional to the reference voltage Vref1; and a first resistor element which is supplied with the constant current, one end of which is coupled to the input terminal of the output circuit and the other end of which is coupled to the second potential.

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: A quadrature modulator has first to fourth transistors, a first node, a second node, and a first output node. A non-inversion in-phase analog signal, an inversion in-phase analog signal, a non-inversion quadrature analog signal, and an inversion quadrature analog signal are supplied to input electrodes of the first to fourth transistors, respectively. Control electrodes of the first to fourth transistors respond to a non-inversion in-phase RF signal, an inversion in-phase RF signal, a non-inversion quadrature RF signal, and an inversion quadrature RF signal, respectively. Output electrodes of the first and second transistors are coupled to the first node, and output electrodes of the third and fourth transistors are coupled to the second node. A first high-pass filter is coupled between the first node and the first output node, and a second high-pass filter is coupled between the second node and the first output node.

Abstract: A reflective exposure mask, a method of manufacturing the reflective exposure mask, and a method of manufacturing a semiconductor device for improving yield in an EUVL (extreme-ultraviolet lithography) using a reflective exposure mask formed to a reflective exposure mask blank are provided. A reflective exposure mask for EUVL includes a low-reflectivity conductor film, a multilayer reflecting film, and an absorber formed on a mask substrate in sequence. The low-reflectivity conductor film has a reflectivity lower than reflectivities of the multilayer reflecting film and the absorber. The absorber forms an absorber pattern in a pattern region of the mask substrate. The multilayer reflecting film has a light-shielding band formed by being removed in a portion surrounding an outer periphery of the pattern region in a groove-like shape. The low-reflectivity conductor film is exposed at a bottom portion of the light-shielding band in a groove-like shape.

Abstract: There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.

Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Abstract: An image processing device includes a main decoding unit that decodes chroma key of main data of input image data, a sub-decoding unit that decodes chroma key of sub-data, a pre-image combining unit that combines the decoded image data before image quality adjustment, an image quality adjusting unit that performs image quality adjustment of image data output from the main decoding unit or composite image data output from the pre-image combining unit, an image combining unit that combines image data after the image quality adjustment and image data output from the sub-decoding unit, and a path control unit that controls a data path so as to perform the image quality adjustment after combining the data when a probability that chroma key is contained in the input image data is high and to perform the image quality adjustment only on the decoded main data when the probability is low.

Abstract: In a power supply unit, a main MOS and a sub MOS connected in parallel in a low-side power MOSFET section, a sensing MOS which is provided on a same semiconductor substrate with the low-side power MOSFET section, detects information corresponding to a load of the low-side power MOSFET section and is smaller in number than the transistors connected in parallel of the low-side power MOSFET section, and a control section for driving the main MOS and the sub MOS based on the information detected by the sensing MOS are provided.

Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.

Abstract: A manual control device with a power generation function includes a manual input unit of a touch sensor type, a control unit that detects a direction input in the manual input unit and performs a control operation according to the direction, a power generation unit that is formed of piezoelectric material for power generation and arranged to a bottom side of the manual input unit, a charge unit that charges electric power from the power generation unit, and a power supply unit that supplies the electric power from the charge unit to the control unit. The operation start control unit supplies an operation instruction to the power supply unit after predetermined delay time since the electric power supply from the power generation unit to the charge unit is detected.

Abstract: An analog-to-digital converter includes a higher-order analog-to-digital converter that outputs a higher-order digital value, a first lower-order converter that converts a first residual signal into a first lower-order digital value, a second lower-order converter that converts a second residual signal into a second lower-order digital value, a calibrator that outputs first and second offset adjustment signals for respectively designating offset adjustment amounts in reversed polarity based on a difference between the first and second lower-order digital values, wherein the first and second lower-order converters set a conversion calibration value based on the first and second offset adjustment signals and calibrate the first and second lower-order digital values based on the conversion calibration value.

Abstract: To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first frequency-divided clock to a selector. The frequency divider outputs a plurality of second frequency-divided clocks each shifted in phase by 1/m of a period based on a control signal of a control circuit. The selector selects two frequency-divided clocks having the closest phase shift from among the first and second frequency-divided clocks. Based on a weighting data signal output from the control circuit, a phase interpolation circuit phase-shifts the frequency-divided clock by a phase shift obtained by dividing the phase difference between the two frequency-divided clocks, and outputs the resultant clock as an output clock.

Abstract: Even when only one of semiconductor packages mounted by carrying out infrared reflow is defective, it is required to carry out infrared reflow again to dismount this defective semiconductor package from a mounting board. At this time, stress of heat is also applied to the other non-defective semiconductor packages. For this reason, if infrared reflow is carried out beyond a number of times of infrared reflow specified for non-defective semiconductor packages, the operation of each non-defective semiconductor package cannot be assured. In this case, it is inevitable to discard the semiconductor packages together with the mounting board. To solve this problem, a magnetic material is passed through a hole penetrating a protection member and a package board and the relevant semiconductor package is fixed over a mounting board by this magnetic material. To supply power to the semiconductor package, electromagnetic induction by coils provided in the package board and the mounting board is used.

Abstract: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.

Abstract: A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.

Abstract: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.

Abstract: An attenuator includes a T-type two terminal pair network including first and second terminals, first, second and third circuits, wherein the first terminal receives an input signal to be attenuated, wherein the first circuit is connected between the first and second terminals, wherein the second circuit is connected between the first circuit and the second terminal and is connected to the first circuit via a node, wherein the third circuit is connected to the node, and a capacitor connected to the node, wherein the capacitance value of the capacitor is variable.

Abstract: There are provided a variable inductor with little degradation in quality factor, and an oscillator and a communication system using the variable inductor. An inductance controller comprising a reactance device with a variable device value, such as, for example, a variable capacitor, is connected to a secondary inductor, magnetically coupled to a primary inductor through mutual inductance. The inductance controller is provided with an inductance control terminal for receiving a control signal for controlling capacitance of the variable capacitor. Inductance of the primary inductor is varied by varying the capacitance by the control signal.

Abstract: A method of manufacturing a semiconductor element including a semiconductor substrate, a conductive post portion provided on the semiconductor substrate to protrude therefrom, and a solder layer provided on the conductive post portion, includes forming on the semiconductor substrate the conductive post portion having a distal end surface curved in a substantially arc shape by electrolytic plating, forming an intermediate solder layer on the distal end surface of the conductive post portion, and reflowing the intermediate solder layer to form the solder layer which has a thickest portion at a top of the distal end surface of the conductive post portion.

Abstract: A head of a hard disc device is retracted to a predetermined position by operating a VCM (Voice Coil Motor) driver. Trouble in a hard disc is detected and retraction is performed even if a short circuit occurs in either of the output line of a VCM driver in an input end of a high potential side or in an input end of a low potential side. A ground short circuit is detected in each side separately and different retracting methods are executed for each case.