Abstract: An exemplary aspect of the present invention is a memory card that includes: a memory that stores data; a driver that modulates the data stored in the memory; a transmitter that transmits the data modulated by the driver to a receiver provided in an external main unit; and an IC chip having the driver and the transmitter formed therein.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.

Abstract: A semiconductor device includes a memory region, and a logic region formed on a substrate, in which a trench recess is provided in the substrate in the memory region. A first transistor is provided in the memory region and a second transistor is provided in the logic region. The first transistor includes a first gate electrode. The first gate electrode is provided to be buried in the recess and to protrude to outside of the recess. The second transistor includes a second gate electrode having a same material as that of the first gate electrode.

Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.

Abstract: An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through then epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.

Abstract: An electrostatic protection circuit includes a first terminal, a second terminal, an input circuit which includes a Metal Oxide Semiconductor (MOS) transistor including a gate, a source, and a drain, the gate as an input terminal being coupled to the first terminal, the source being coupled to the second terminal, an electrostatic protection element connected to the drain, the electrostatic protection element including a first electrostatic protection element, and a second electrostatic protection element connected between the first terminal and the second terminal.

Abstract: Provided is a method for the effective silylation treatment of a silica-based porous insulating film having a plurality of pores. The method of producing a silylated porous insulating film (204c) includes a process whereby a porous insulating film (204b) having a plurality of pores is formed, and a process wherein a silylating material vapor (210) obtained by vaporizing silylating material containing organic silane compound having a hydrophobic group and polymerization inhibitor which inhibits the auto-polymerization of the organic silane compound is caused to act upon the porous insulating film (204b).

Abstract: A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

Abstract: The semiconductor device having a bonding pad is provided. The bonding pad enables highly reliable connection and high flexibility of the selection of the area to be bonded. The semiconductor device includes a bonding pad and an area designation marking. The bonding pad includes a first region, a second region and a third region formed between the first region and the third region. The area designation marking includes a first notch for designating a first boundary of the first region and the third region and a second notch for designation a second boundary of the second region and the third region. Any of the first region and the second region can be used as the region where the scratch formed by a probing process is to be formed.

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract: The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink.

Abstract: In a wafer, a first chip region and a second chip region are separated from each other by a dicing region. The dicing region includes: a first center region; a first intermediate region located on the first chip region's side of the first center region; a second intermediate region located on the second chip region's side of the first center region; a first outer region located on the first chip region's side of the first intermediate region; and a second outer region located on the second chip region's side of the second intermediate region. Surfaces of the first and second intermediate regions are respectively covered by bank-shaped resin films extending in a longitudinal direction of the dicing region. Respective surfaces of the first center region, the first outer region and the second outer region are not covered by resin films.

Abstract: A contactless IC card which ensures the reliability of an IC chip mounted therein. Even if the distance between the contactless IC card and a reader/writer is too short, the card prevents an excessive voltage from being applied to the IC chip so that breakdown or reliability deterioration of the circuitry of the IC chip does not occur. The body of the contactless IC card has two interconnection substrates stacked between two external sheets. A first antenna coil formed on one interconnection substrate and a second antenna coil formed on the other interconnection substrate are opposite in winding direction. The number of turns of the second antenna coil is larger than that of the first antenna coil. Therefore, when the IC card comes close to the reader/writer, the voltage between two terminals of the IC chip is always smaller than the voltage induced in the second antenna coil.

Abstract: A semiconductor device includes a substrate, a semiconductor chip that is bonded to one of the faces of the substrate via bumps, and has a device formation face facing the one of the faces, and a resin that fills the space between the device formation face of the semiconductor chip and the one of the faces of the substrate. The resin includes: a first resin that is formed in a formation region of bumps placed on the outermost circumference of the bumps, and is formed inside the formation region, and a second resin that is formed outside the first resin. The thermal expansion coefficient of the substrate is higher than the thermal expansion coefficient of the first resin. The thermal expansion coefficient of the second resin is higher than the thermal expansion coefficient of the first resin.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a semiconductor substrate, a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer, and a charge trapping layer that is formed between the channel region and the second gate electrode, and that includes a second insulating layer for trapping a charge. Data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer. The first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor.

Abstract: Provided is a synchronization detection circuit including: a multiphase clock generation circuit which includes a phase locked loop circuit that generates multiphase clock signals having a plurality of different phases, based on a reference clock signal, and which generates high-speed multiphase clock signals having a frequency obtained by multiplying a frequency of the reference clock signal, and low-speed multiphase clock signals having a frequency obtained by dividing a frequency of the high-speed multiphase clock signal; and a synchronous clock specifying circuit that specifies a clock signal synchronized with a synchronous signal from among the multiphase clock signals, and generates a synchronous position signal indicating a synchronous position of the synchronous signal, based on a comparison result between the synchronous signal and the high-speed multiphase clock signals and a comparison result between the synchronous signal and representative clock signals selected from the low-speed multiphase cloc

Abstract: The wiring board includes: a base material; a copper pattern which is formed in one surface of the base material, and made of a first metal; and a first nickel land and a second nickel land which are formed over the copper pattern in contact with the copper pattern, and made of a second metal having a higher ionization tendency than that of the first metal, wherein a groove reaching the base material is formed in the copper pattern around a region overlapping the first nickel land at least when seen in a plan view.