Abstract: The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

Abstract: A dry film includes a first solder resist film, a second solder resist film and a supporting film. The first solder resist film includes first particles of first elastomer. The supporting film supports the first solder resist film and the second solder resist film. Adhesion strength of a surface of the second solder resist film is weaker than adhesion strength of a surface of the first solder resist film at a glass transition point of the first elastomer. According to the dry film, it is possible to form a wiring board including a solder resist film which is arranged at a surface of the wiring board and hard to be adhered to a body such as a die upon heating.

Abstract: A photosensitive resin film is formed on a protective insulating film. Next, a plurality of bump cores is formed on the protective insulating film along a first straight line by exposing and developing the photosensitive resin film. Next, a plurality of bumps, and a plurality of interconnects that connects each of the plurality of bumps to any of the electrode pads are formed by selectively forming conductive films on a plurality of bump cores, a plurality of electrode pads, and the protective insulating film. In the step of forming a plurality of bump cores, a region bordering on the interconnect on the lateral faces of the bump core is formed to have a gentler slope than that of a region intersecting the first straight line, by exposing the photosensitive resin film only one time using a multi-gradation mask.

Abstract: A nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention including, a first gate electrode formed above a semiconductor substrate via a first insulating film, having a projecting part which projects in upper direction with a certain width; a second gate electrode formed beside a side surface of the first gate electrode via a second insulating film; two side walls having insulation properties formed on a side surface of the second gate electrode and a side surface of the projecting part respectively; and a silicide layer formed on an upper surface of the projecting part and a part of a surface of the second gate electrode, wherein a width of the projecting part is smaller than a width of the first gate electrode below the projecting part.

Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.

Abstract: A semiconductor apparatus operates based on a first voltage, a second voltage lower than the first voltage, and a third voltage in between the first and second voltages, and includes an output circuit including at least one transistor where a signal having an amplitude ranging from the second to first voltages is input to a gate, and a control circuit that generates a first control signal controlling a gate voltage of a transistor included in the output circuit, a second control signal controlling a voltage in a back-gate region of the transistor, and a third control signal controlling a voltage in a deep well region. The control circuit sets a voltage difference between the first and second control signals to be equal to or smaller than the larger one of a voltage difference between the first and third voltages and a voltage difference between the second and third voltages.

Abstract: Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.

Abstract: A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.

Abstract: It is desired to provide an electronic device which can be easily taken out of a mold after a resin sealing processing. The electronic device include: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed to cover the insulation layer and the wiring and including particles of an elastomer. An asperity is formed on a surface of the solder resist layer.

Abstract: A method of manufacturing a semiconductor chip with a conductive adhesive layer including steps of: forming a conductive adhesive layer on back side of a wafer on which a semiconductor element is formed; laminating a flexible substrate on back side of the conductive adhesive layer; forming a dicing groove which reaches from a front of the wafer to the conductive adhesive layer and a bottom of which is in the conductive adhesive layer; pressing from back side of the flexible substrate in such a way that the conductive adhesive layer is cut with the dicing groove as an origin point; and separating the flexible substrate from the conductive adhesive layer.

Abstract: A drive device according to the present invention includes a plurality of output amplifier circuits that are connected in parallel, a bias wire that supplies a bias voltage from a bias voltage supply source to the plurality of output amplifier circuits, a power supply wire that supplies a power supply voltage from a power supply voltage supply source to the plurality of output amplifier circuits, and a correction unit that superposes an offset voltage on the bias voltage so that a voltage difference between the power supply voltage and the bias voltage supplied to the plurality of output amplifier circuits is to be desirable.

Abstract: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.

Abstract: A semiconductor device includes a substrate, a low dielectric constant layer formed on the substrate, a first protection insulating layer formed on the low dielectric constant layer, and a trench with an interconnect embedded in formed in the first protection insulating layer and the low dielectric constant layer. The sidewall of the trench has a structure that the surface of the first protection insulating layer protrudes from the surface of the low dielectric constant layer, a second protection insulating layer formed by a chemical vapor deposition technique is embedded at the surface of the low dielectric constant layer in an area below the first protection insulating layer, and the sidewall of the trench is constituted by the second protection insulating layer and the first protection insulating layer.

Abstract: A split gate nonvolatile semiconductor storage device includes: a substrate; a floating gate; a control gate; a first source/drain diffusion layer; a second source/drain diffusion layer; and a silicide. The floating gate is formed on the substrate through a gate insulating film. The control gate is formed adjacent to the floating gate through a tunnel insulating film. The first source/drain diffusion layer is formed in a surface region of the substrate on a side of the floating gate. The second source/drain diffusion layer is formed in a surface region of the substrate on a side of the control gate. The silicide contacts the first source/drain diffusion layer.

Abstract: A nonvolatile semiconductor memory device has: a first source/drain diffusion region; a second source/drain diffusion region; a channel region between the first source/drain diffusion region and the second source/drain diffusion region; a first charge storage layer formed on the channel region; a second charge storage layer formed in a same layer as the first charge storage layer and electrically isolated from the first charge storage layer; a first gate electrode; and a second gate electrode electrically isolated from the first gate electrode. The first charge storage layer includes a first memory section and a second memory section. The second charge storage layer includes a third memory section and a fourth memory section. The first gate electrode is formed on the first memory section and the third memory section. The second gate electrode is formed on the second memory section and the fourth memory section.

Abstract: The semiconductor device includes a substrate; a semiconductor chip mounted over the substrate; resin encapsulating the semiconductor chip; and a heat dissipation material that is arranged over the semiconductor chip and in contact with the resin, wherein the resin includes a first resin region made of a first resin composition, a second resin region made of a second resin composition, and a mixed layer that is formed between the first and second resin regions and obtained by mixing the first resin composition and the second resin composition.

Abstract: A CCD image sensor includes a photo-diode region segmented by an element separation region; and a CCD register connected with the photo-diode region through a transfer gate. The photo-diode region includes a plurality of tapered portions, and each of the plurality of tapered portions is formed to become wider in a direction of the transfer gate.

Abstract: The data processor provides an access protection with higher reliability during data transfer control according to a transfer condition set by CPU. The data processor has: CPU; a memory management section operable to control data transfer by CPU; and a transfer controller operable to control data transfer. The transfer controller holds identification information which the memory management section uses for access protection. When producing an address for transfer according to the setting of CPU, the transfer controller starts data transfer on condition that the identification information corresponding to the address for transfer matches the identification information of CPU at the setting of a transfer condition, etc.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: A data transfer control device in accordance with an exemplary aspect of the present invention includes a first communication unit that processes data transfer with a peripheral device, and a second communication unit that processes data transfer with a host device, wherein one of the first and second communication units serves as a preferential communication unit whose data transfer should have a high priority, and another of the first and second communication units serves as a non-preferential communication unit, when the data transfer is being performed in the preferential communication unit, the preferential communication unit notifies the non-preferential communication unit that the data transfer is being performed, and when the non-preferential communication unit is being notified that the data transfer is being performed from the preferential communication unit, the non-preferential communication unit puts the data transfer in the non-preferential communication unit on hold.