Abstract: A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in a logic region, and having a second source/drain region containing at least arsenic as an impurity, wherein each of the first source/drain region and the second source/drain region has a silicide layer respectively formed in the surficial portion thereof, and the first source/drain region has a junction depth which is determined by phosphorus and is deeper than the junction depth of the second source/drain region.

Abstract: A voltage-controlled oscillator includes a delay circuit. The delay circuit includes a first buffer inverter which receives one of the differential input signal and outputs an other of the differential output signal, a second buffer inverter which receives the other of the differential input signal and outputs the one of the differential output signal, a first latch inverter which receives the one of the differential output signal, and includes an output connected to an output of the first buffer inverter, and a second latch inverter which receives the other of the differential output signal, and includes an output connected to an output of the second buffer inverter. The first latch inverter and the first buffer inverter receive a current produced from different voltage-current conversion circuits.

Abstract: A delay circuit includes a ring oscillator and a control circuit. The control circuit includes an edge detector that outputs a first control signal in response to a rising edge or a falling edge of an input signal, and a counter that counts the number of pulses of an output pulse signal output from the ring oscillator and outputs a second control signal upon reaching a predetermined count number. The control circuit performs control to make the ring oscillator oscillate in response to the first control signal and to output the input signal in response to the second control signal.

Abstract: An arithmetic circuit includes a NOR circuit for outputting 1-bit inverted logical OR sf from all of a first bit group x(6) to x(10) containing 0 or more high-order bit of a path metric value composed of a plurality of bits, an inverter for inverting each bit of a second bit group x(2) to x(5) and outputting a third bit group rs(0) to rs(3), an AND circuit for outputting a fourth bit group ns(0) to ns(3) that contain results of calculating a logical AND of sf and rs(0) to rs(3), and a CF output section for outputting a correction factor CF based on ns(0) to ns(3).

Abstract: A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided between the current mirror circuit and the fuse data holding unit. The bias voltage generating circuit applies the bias voltage to the control circuit.

Abstract: A bonding apparatus includes: a storage unit that stores bonding conditions of a ball; a detection unit that detects a first position on a Z axis of a capillary with the ball coming into contact with a semiconductor element and detects a second position on the Z axis of the capillary when the ball at the tip end of the capillary is bonded to the semiconductor element; a calculation unit that calculates a collapse amount of the ball which is a difference between the first position and the second position detected by the detection unit and a bonding time and calculates a collapse amount of the ball for a predetermined period; and a first adjustment unit that adjusts the bonding conditions when the collapse amount of the ball for a predetermined period is outside a predetermined numerical range.

Abstract: A parasitic element extracting system includes: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; and a marker producing section configured to generate a marker to indicate a via-contact connecting the upper interconnection layers and the lower interconnection layers. An upper layer parasitic element list producing section is configured to generate an upper layer parasitic element list by extracting parasitic elements in the upper interconnection layers based on a first criterion, and a lower layer parasitic element list producing section is configured to generate a lower layer parasitic element list by extracting parasitic elements in the lower interconnection layers based on a second criterion which is different from the first criterion.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt0 of the terminal region between the plurality of contacts and the main body by the following formula, where ?0, L?0, W?0 are fitting parameters; L? is a length of the terminal region in the longitudinal direction of the well resistor; and W? is a width of the terminal region in the width direction of the well resistor.

Abstract: A source driver having a cascade connection configuration that drives signal lines of a display device according to a plurality of signals transmitted by a mini-LVDS interface from a controller during a predetermined period corresponding to a cascade signal received from a preceding stage, the source driver including a first reception circuit receiving a first signal of the plurality of signals; a second reception circuit receiving a second signal of the plurality of signals; and an enable control circuit that controls each of the first and second reception circuits to one of an active state and a standby state; in which the enable control circuit sets the second reception circuit to the active state according to the cascade signal received from the preceding stage, and sets the first and second reception circuits to the standby state according to a cascade signal output by the source driver to a subsequent stage.

Abstract: The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: A switching power supply device performs a stable operation with fast response for a semiconductor integrated circuit device. A capacitor is provided between the output side of an inductor and a ground potential. A first power MOSFET supplies an electric current from an input voltage to the input side of the inductor. A second power MOSFET turned on when the first power MOSFET is off allows the input side of the inductor to be of a predetermined potential. A first feedback signal corresponding to an output voltage obtained from the output side of the inductor and a second feedback signal corresponding to an electric current flowed to the first power MOSFET are used to form a PWM signal. The first power MOSFET has plural cells of a vertical type MOS-construction.

Abstract: A semiconductor device in accordance with the present invention includes a diode 7 that is formed on a semiconductor substrate and serves as a temperature detection element to detect abnormal heat generation, and a thermal conduction layer 102 that is formed between the diode 7 and the semiconductor substrate and has a thermal conductivity higher than that of the semiconductor substrate. In this way, heat generated in a heat generating portion can be swiftly and uniformly conducted over the entire temperature detection element composed of the diode 7 with efficiency. In this way, a semiconductor device capable of detecting temperature with excellent response by the temperature detection element and its manufacturing method can be provided.

Abstract: High-accuracy overcurrent detection is performed, while a loss resulting from the current detection is significantly reduced. A switch section outputs the voltage between the both terminals of a current detection resistor using an AND signal between an output signal from a hysteresis comparator and an output signal from a pre-driver. The voltage is filtered by an electrostatic capacitor element and a resistor, and inputted to a comparator. The comparator makes a comparison between the signals inputted to the two input terminals thereof, and outputs the result of the comparison to a digital filter. When an overcurrent begins to flow in a power supply unit, the levels of the voltages inputted to the two input terminals of the comparator are inverted so that the comparator outputs an inversion signal to the digital filter. The digital filter outputs a detection signal to an overcurrent detection circuit when an arbitrary time has elapsed.

Abstract: A switching regulator includes first and second transistors, which are provided in series between power sources respectively having first and second potentials, and which convert a direct current voltage of a potential difference between the first and the second potentials into an alternating current voltage, and a control circuit. The control circuit includes a comparator which compares the alternating current voltage and a threshold voltage in a period when the second transistor is to be on, and receives a predetermined voltage, at least immediately before the period in which the second transistor is to be on, the predetermined voltage being farther than a midpoint potential of the first and second potentials from the threshold voltage.

Abstract: A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film.

Abstract: A semiconductor device includes a current supply section configured to control a current flowing through a load circuit; an overcurrent detecting section configured to detect based on the current, that an overcurrent flows through the load circuit, to output an overcurrent signal; and an overheat detecting circuit configured to detect that a peripheral temperature exceeds a detected temperature; in response to the overcurrent signal, and output an overheat detection signal. The overheat detecting circuit has a hysteresis to the detection temperature, and the detection temperature contains an overheat detection temperature used to detect an overheat state and a recovery temperature used to detect to have escaped from the overheat state.

Abstract: The semiconductor integrated circuit includes a first oscillator, a second oscillator (PLL), a third oscillator (ring oscillator), a selector that switches, in turn, based on a clock of the third oscillator, and outputs a clock of the first oscillator or a clock of the second oscillator, and a determination circuit that counts up or counts down the clock output from the selector, based on the clock of the third oscillator, determines the correspondence of the clock output from the selector and the clock of the third oscillator, based on a result of the counting up or the counting down, and determines whether either of the clock output from the selector or the clock of the third oscillator occur an abnormal oscillation.

Abstract: The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.

Abstract: It is desired to provide an electronic device which can be easily taken out of a mold after resin sealing processing. The electronic device includes: an insulating layer; a wiring layer formed on a surface of the insulating layer; a first solder resist formed to cover the insulating layer and the wiring layer and including a particle of a first elastomer; and a second solder resist formed to cover a surface of the first solder resist. A surface of the second solder resist has smaller adhesive strength than the surface of the second solder resist at a glass transition point of the first elastomer.