Abstract: A visual inspection apparatus includes a stage on which a FCBGA type semiconductor package having a lid is placed, a camera located above the stage, a coaxial illumination device located between the camera and the stage, an oblique illumination device located between the camera and the stage, and a control device. The control device is configured to irradiate the FCBGA type semiconductor package with illumination lights by the coaxial illumination device and the oblique illumination device, capture the FCBGA type semiconductor package by the camera to obtain the captured image, integrate a number of pixels of a predetermined pixel value by a binarization process of the captured image to obtain a determination value, and compare the determination value with a predetermined value to determine a non-defective product or a defective product.

Abstract: A driver for driving an electromechanical device having a solenoid and a mechanical switch. The driver includes an input port, a ground port, first and second output ports connectable to the electromechanical device; and two power switches. A controller operates in a first mode to charge the solenoid and close the mechanical switch, a second mode to maintain the mechanical switch closed, and a third mode to discharge the solenoid and open the mechanical switch. In the first and second modes, the low-side power switch is on and the high-side power switch is controlled to switch between an on-state and an off-state by the controller. In the on-state a path is formed between the input port and ground via the high-side and low-side power switches, and the solenoid. In the off-state a path is formed between ground and ground via a ground diode, the solenoid and the low-side power switch.

Abstract: Systems, apparatuses, and methods for detecting a foreign object on a wireless power charging region are described. A circuit can detect an object inductively coupled to a wireless power transmitter. The circuit can further measure an input parameter prior to a power transfer stage, the input parameter can be one of an input current and an input power. The circuit can further compare the measured input parameter with a predetermined value. The circuit can further determine whether the object is a foreign object or the wireless power receiver based on a result of the comparison between the measured input parameter with the predetermined value.

Abstract: Systems and methods for amplifying a signal is described. A circuit may convert an input radio frequency (RF) signal into a first RF signal with power level matching a power capacity of a first transistor of a first size in a carrier amplifier stage, a second RF signal with power level matching a power capacity of a second transistor of the first size in a peaking amplifier stage, and a third RF signal with third power level matching a power capacity of a third transistor of a second size in another peaking amplifier stage. The circuit may amplify the first, second, and third RF signals to generate first, second, and third amplified RF signals, respectively. The circuit may combine the first, second, and third amplified RF signals, into an output RF signal that is an amplified version of the input RF signal.

Abstract: A method and position sensor system for detecting an error of a position sensor system are provided. The method and position sensor system implementing the steps of: determining the period length of three previous signal periods of the position signal, comparing the period lengths of the three previous signal periods of the position signal to detect a constant velocity position signal, a constant accelerating or decelerating position signal or position signal with a constant jerk, predicting the period length of the next signal period of the position signal, transferring the predicted period length of the next signal period to a predicted position signal for the next signal period, and comparing the predicted position signal with the actual position signal to detect errors in the position signal of the next signal period.

Abstract: The semiconductor device 10 receives an input signal given from the signal generating unit provided externally by a plurality of receiving units, a receiving unit 12, 13 for generating a plurality of received signals from the received input signal, a plurality of received signals by comparing, an error determination unit 14 for outputting an error notification to the upper system in response to the error between the channels that occurs between the received signals becomes equal to or greater than the threshold value, the threshold count value is stored and a threshold count register 17, the error determination unit 14 waits for the departure of the error notification until the period specified by the threshold count value has elapsed.

Abstract: An analog to digital converter for converting an analog signal to a digital signal by sampling the analog signal to generate the digital signal, the analog to digital converter being configured to acquire a first sample comprising a first plurality of bits that is representative of the digital signal, determine one or more bit positions within the first plurality of bits that are variable, determine one or more bit positions within the first plurality of bits that are static, and acquire a second sample after having acquired the first sample, the second sample comprising a second plurality of bits that is representative of the digital signal, wherein for the acquisition of the second sample at least a portion of the one or more bit positions that are variable have their bit values generated by sampling of the analog signal, and each of the one or more bit positions that are static have their bit values set to the same bit value as the bit value of the corresponding bit position in the first sample.

Abstract: A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film.

Abstract: In a semiconductor device, an arithmetic circuit of a chip on a first stage performs a predetermined arithmetic operation on an input N-bit (N=4) selection signal. Similarly, an arithmetic circuit of each of chips on second and subsequent stages among chips on a total of M stages (M>N?2, M=16) performs a predetermined common arithmetic operation on an operation result of the arithmetic circuit of the chip on the preceding stage. A determination circuit provided in each chip performs a predetermined common logic operation on a bit string of the N-bit signal, which is the operation result of the corresponding arithmetic circuit, thereby determining whether it is the chip selected by the selection signal.

Abstract: The designing method according to an embodiment of the present invention is a method of designing a transmission line portion coupled between a transmission unit and a receiving unit, and transmitting a signal from the transmission unit to the receiving unit. Also, one-data-width distance is obtained by converting one-data-width interval, which is corresponding to a sampling period of an equalizer provided in one of the transmission unit and the receiving unit, to a distance. Further, a first reflection source for reflecting the signal is arranged at a position of the transmission line portion, where is corresponding to a ½-data-width distance corresponding to a half of the one-data-width distance. Here, the position corresponds to a grid point where a row grid line drawn on a screen used in the designing method and a column grid line drawn on the screen intersect with each other.

Abstract: A sensor system and an update server perform a method for updating the sensor system. The update server performs steps of retrieving a pre-shared sensor key associated with the sensor system, calculating a server signature based on update data and the retrieved sensor key, and transmitting the update data and the calculated server signature to the sensor system. On the other hand, the sensor system performs steps of receiving the update data and the calculated server signature, retrieving the pre-shared sensor key stored in a register, calculating a sensor system signature based on the update data and the pre-shared sensor key, comparing the sensor system signature with the server signature and processing the update data if the sensor system signature and the server signature are identical.

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

Abstract: A semiconductor device includes a first well region, a second well region, a body region, and a cathode region. The impurity concentration of the body region is higher than the impurity concentration of the first well region, and the impurity concentration of the second well region is higher than the impurity concentration of the body region. In plan view, the body region includes the cathode region, and the cathode region includes the second well region. The cathode region configures a cathode of a Zener diode, and the first well region, the second well region, and the body region configure an anode of the Zener diode.

Abstract: A slave device for IO-Link communication with a master device, wherein the master device and the slave device operate on a common basic timing, the slave device including at least one Universal Asynchronous Receiver Transmitter (UART) module configured to detect an INIT request sent from the master device during communication setup, calculate an actual timing of the master device from the INIT request and correct an initial timing of the slave device to an actual timing of the slave device based on the actual timing of the master device.

Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

Abstract: An AD converter includes a plurality of analog input terminals, a reference signal generation circuit that generates an analog reference signal, a sample-and-hold unit that includes a plurality of sample-and-hold circuits sampling the analog reference signal or one of analog input signals from the analog input terminals, a control unit that controls the sample-and-hold unit, and a conversion unit that converts an output signal from the sample-and-hold unit into a digital signal. The control unit controls the sample-and-hold unit to perform the output operation for analog input signal and the sampling operation for the analog reference signal.

Abstract: In each of n twin cells of n first sense amplifier, a current path is formed between a power supply line and one memory cell having a small or large cell current in a data readout state of two memory cells. A second sense amplifier generates erase verify information indicating whether all stored data in the memory cells of the n twin cells are in an erase state at the same level, based on a verify current flowing through a power supply line as a sum of currents of the n first sense amplifiers.

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

Abstract: A DC-DC power converter has a ground terminal, an input terminal for receiving an input voltage and an output terminal for providing an output voltage with a target conversion ratio. The power converter includes a coupled inductor having a first winding and a second winding coupled to the output terminal; a first flying capacitor coupled to a first inductor and to the second winding; a second flying capacitor coupled to a second inductor and to the first winding; an input capacitor coupling the input terminal to the ground terminal; an output capacitor coupling the output terminal to the ground terminal; a network of switches; and a driver adapted to drive the network of switches with a sequence of states during a drive period, wherein the sequence of states forms a switching cycle.

Abstract: A differential digital power amplifier to drive an RFID antenna with a sinusoidal output current with an RFID frequency which differential digital power amplifier comprises: a digital control section to output digital wave-forming bits to a first group of driver blocks and a second group of driver blocks wherein a switch between the source contact of a first source follower transistor and the source contact of a second source follower transistor to short circuit these source contacts to unload/load gate-source capacitances of a drain extended PMOS transistors with charge carriers used to load/unload gate-source capacitances of the drain extended NMOS transistors to reduce the driver current needed at gate contacts of the drain extended PMOS transistors and drain extended NMOS transistors.