Abstract: The access control circuit writes to the first storage unit a context information transmitted in one cycle from the CPU through the first bus, a context number identifying the context information, and a link context number identifying the context information transmitted from the CPU prior to the interrupt when the request for evacuating the task context information is received by the interrupt. After writing to the first storage unit, the access control circuit transfers the data including the context information and the link context number stored in the first storage unit to the second storage unit in a plurality of cycles through the internal bus (second bus) in association with the context number stored in the first storage unit.

Abstract: A monitor circuit monitors a gate potential applied to a gate of a high-side transistor or monitors an output potential generated at an output terminal and generates either one or both of a high-side sampling timing and a high-side holding timing based on the monitored result. A current detection circuit detects an inductor current flowing in an inductor and generates a first detection voltage proportional to the inductor current. A sample-and-hold circuit starts a sampling operation of the first detection voltage in response to the high-side sampling timing and starts a holding operation of the first detection voltage in response to the high-side holding timing so as to output a second detection voltage.

Abstract: A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

Abstract: There is provided a retrieval memory that can easily manage address information. A retrieval memory which retrieves whether or not inputted retrieval data matches entry data stored in a memory cell array and outputs address information corresponding to matched entry data includes a plurality of retrieval blocks and an output control unit for outputting the address information. The address information includes a block address for specifying at least one of the retrieval blocks and a logical address corresponding to entry data in the specified retrieval block. The output control unit outputs address information that is reset so that the address information corresponding to the entry data becomes continuous in an address space based on a size of the entry data.

Abstract: An additional test pattern acquiring unit acquires a test pattern, which is not yet executed to the semiconductor device serving as a target of executing an additional test among test patterns stored in a test pattern information DB, as an additional test pattern with reference to a semiconductor manufacturing history information DB. Also, an additional test transmitting unit transmits the additional test pattern acquired by the additional test pattern acquiring unit to the semiconductor device serving as the target of the additional test through a network. An additional test result acquiring unit acquires a test execution result together with an ID of the semiconductor device, and a registration unit registers identification information of the executed test pattern, an execution result of the test pattern, and an execution timing of the test in a semiconductor product history information DB so as to be associated with the acquired ID of the semiconductor device.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.

Abstract: An object of the present disclosure is to continue optical image stabilization even in the case where a correcting lens is positioned near a mechanical end. An optical image stabilization module used to control a camera module adjusts the position of a correcting lens and the like used for optical image stabilization while executing the optical image stabilization during an exposure period. An image distortion accompanying the position adjustment of the correcting lens can be corrected by, for example, an electronic image stabilization module.

Abstract: In the field of wireless communication, a technique for inhibiting a disconnection while also inhibiting a communication slow-down is provided. A wireless communication device includes: a communication module configured to be capable of communicating with another wireless communication device through plural channels in a first mode with a first code strength and in a second mode with a second code strength higher than the first code strength; a strength measurement unit which measures a received signal strength; a channel detection unit which detects unused channels; and a control device which switches the communication mode of the communication module between the first mode and the second mode based on the strength measured by the strength measurement unit of a signal received from another wireless communication device and the number of unused channels detected out of plural channels by the channel detection unit.

Abstract: A semiconductor device is provided which can detect a fluctuation of a power supply voltage. The semiconductor device includes a counter circuit that outputs a signal when a period during which a power supply voltage of a system to be monitored is lower than or equal to a first voltage value exceeds a predetermined time, a first flag circuit that sets a first flag based on the signal, a second flag circuit that sets a second flag when the power supply voltage becomes a second voltage value or lower, and a circuit that outputs a reset signal that resets the system when both the first and the second flags are set. The first voltage value and the second voltage value are higher than a minimum voltage that guarantees normal operation of the system. The first voltage value is higher than the second voltage value.

Abstract: A semiconductor device and electronic control device capable of shutting off the reverse current flow from a load to a power supply is provided. The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(?) is higher than the potential of the positive power supply terminal Pi2(+).

Abstract: When contents of UFSHCI standard are directly implemented in a UFS host, a problem may occur such that read/write operations of a UFS device stop or contents of data are destroyed. A semiconductor device has a UFS host controller that performs data transfer with a universal flash storage (UFS) device. The semiconductor device includes a Run-Stop register that sets the UFS host controller into a processing possible state, a Door bell register that instructs the UFS host controller to perform transfer, and a ready bit that indicates whether or not the UFS host controller can perform processing of transfer request. When the Run-Stop register is cleared while the data transfer is in process, the UFS host controller prevents a next data transfer from being registered until the data transfer is completed.

Abstract: An apparatus and method for mapping timer channels to protection groups. One embodiment of the method can be implemented in a microcontroller unit (MCU) that comprises a central processing unit (CPU) coupled to a plurality of timer channels and a plurality of programmable group output disable (PTGOD) circuits. The CPU can select a first group of the timer channels to respond to an assertion of a first output disable signal from a first of the PTGOD circuits. Each timer channel of the first group can disable an output signal in response to receiving the assertion of the first output disable signal.

Abstract: One or more embodiments are directed to a battery charger that can support multiple battery applications with a single USB type-C port. The architecture can be easily extended to support more applications such as those including two or more USB Type-C ports by adding additional voltage regulators. Additionally, the architecture can easily be extended to support additional batteries by adding corresponding battery chargers. Some embodiments enable supplying two or more system voltages and charging two or more batteries simultaneously using a single adapter and/or port. Other embodiments enable supplying voltage to On the Go devices from two or more batteries simultaneously.

Abstract: A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: A semiconductor device has a memory circuit and a logic circuit coupled with a memory circuit. the memory circuit included a memory array in which memory cells are arranged in a matrix, an input/output circuit for writing data to the memory cells and reading data from the memory cells, and a control circuit for generating a control signal for controlling the input/output circuit. In a test operation for testing the logic circuit, the input/output circuit receives a test data. The control circuit raises and lowers the control signal based on a rising and a falling of an external clock signal, thereby the test data is output to the logic circuit via the input/output circuit.

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Abstract: A control device capable of accurately detecting a rotor rotation angle is provided. The control device includes variable resistors R1 to R4 for converting the currents flowing in the four-phase coils of the current detection resolver into voltages, two differential amplifiers for a first phase signal of the voltage difference between the detection voltages of the variable resistors R1 and R3, and a second phase signal of the voltage difference between the detection voltages of the variable resistors R2 and R4 respectively, two phase shifters for shifting the phase of the first phase signal and the second phase signal respectively, a synthesizer for a phase modulation signal by synthesizing the phase shifted first phase signal and the phase shifted second phase signal, and an adjuster for adjusting the resistance values of the variable resistors R1 to R4 based on the width of the envelope of the phase modulation signal.

Abstract: A fixed logic integrated circuit is disclosed. The integrated circuit comprises a unique code generator configured to generate a code having a value which is intrinsically unique to the integrated circuit, an enrolment pattern generator configured to generate an enrolment pattern based on the unique code. The integrated circuit is configured to transmit the enrolment pattern to an external enrolment device and to receive enabling data from the external enrolment device. Optionally, the integrated circuit may include memory for storing remotely-generated enabling data. The integrated circuit comprises a configuration file generator configured to generate configuration data using the remotely-generated enabling data and the unique code, and a feature activation module configured to activate and/or disable features of the integrated circuit and/or customise the integrated circuit in dependence upon the configuration data.

Abstract: An semiconductor device capable of suppressing an increase in layout area can be provided. According to one embodiment, the semiconductor device comprises a transistor including a drain formed in a main surface portion of the semiconductor substrate, a source formed in a main surface portion, and a gate for controlling the current between the drain and the source, a drain wiring connected to the drain through the contact, and a passing wire disposed between the source wiring connected to the source through the contact and insulated from the drain, the source, and the gate.