Abstract: Various exemplary embodiments are directed to methods including obtaining an input sample magnitude, filtering the obtained input sample magnitude, generating a sample-to-sample difference based on the filtered input sample magnitude, and engaging an actuator in accordance with a determination that the sample-to-sample difference satisfies a rate threshold.

Abstract: There is a need to provide a semiconductor device and an electronic control system including the same while the semiconductor device is capable of continuing normal operation even when a negative surge voltage is applied. According to an embodiment, a driver IC includes an output transistor, a driver control circuit, a negative potential clamp circuit, and an ESD protection circuit. The output transistor is provided between a battery voltage terminal and an output terminal coupled to a load. The driver control circuit switches on-off state of the output transistor by controlling a gate voltage of the output transistor with reference to a voltage of the output terminal. The negative potential clamp circuit turns on the output transistor regardless of control from the control circuit when a negative voltage lower than a predetermined voltage is applied to the output terminal.

Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: In the conventional semiconductor device, the power consumed in ternary serial data communication cannot be reduced. According to one embodiment, the semiconductor device has a the transmission processing circuit 10 that converts the binary representation of binary Transmitted data Dbin_TX to a ternary transmitted data Dter_TX represented as a ternary number and generates a transmitted signal corresponding to this ternary Transmitted data Dter_TX, wherein the transmission processing circuit 10 verifies the frequency of occurrence of the values included in the ternary transmitted data Dter_TX, assigns the signal change pattern with the highest state transition to the transmitted signal logical level corresponding to the lowest occurrence value, and generates a transmitted signal.

Abstract: One or more embodiments are directed to a multiport power delivery architecture that reduces the cost and maximizes the power utilization. According to some aspects, an adapter power add-up feature of the embodiments can combine the power of two or more adapters. The total power can be used to support CPU Turbo events and Quick Charge function. In one aspect, one charger operates as voltage source or current source and the other(s) as current source(s). When the system demand is high enough for all chargers may operate as current sources, the battery will supply the rest of the system demand. The proposed implementation of adapter power add-up feature can enable simple control scheme. Customers can set up BGATE control priorities to determine which charger to handle the BGATE control.

Abstract: A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn includes a first electrode such as an emitter. The apparatus also includes a first conductor sintered to an electroplated second conductor such as a solid top terminal. Importantly, the first conductor is electrically coupled to the first electrode.

Abstract: To provide a semiconductor device capable of having improved adhesion between a plating film and a wiring layer. A method of manufacturing the semiconductor device includes a step of forming a wiring layer having a surface covered with an oxide film, a step of removing a portion of the oxide film by dry etching to form, in the oxide film, a first opening for exposing a portion of the wiring layer, a step of forming a passivation film covering the wiring layer, is provided with a second opening communicated with the first opening, and is made of an insulating resin material, and a step of growing a plating film on the wiring layer exposed from the first and second openings.

Abstract: A semiconductor device has a drive transistor coupled to a load and a current detection circuit. The current detection circuit includes: an operational amplifier amplifying a potential difference between voltage of a first terminal and voltage of a second terminal; a sense transistor passing sense current between the first terminal and the drive transistor; a voltage supply circuit having a first current source and supplying voltage higher than voltage supplied to the grounding voltage terminal to the second terminal; a third terminal outputting current based on the sense current; a second current source coupled between the third terminal and the grounding voltage terminal; and a current source control circuit controlling current of the first and second current sources. Detection current detected by the current detection circuit is current obtained by subtracting the current of the second current source from the current based on the sense current.

Abstract: One or more embodiments are directed to a battery charger that can support multiple battery applications with a single USB type-C port. An architecture according to one or more embodiments includes a single charger transferring power to multiple battery stacks. The architecture according or one or more embodiments includes a plurality of battery stacks each respectively housed in a distinct electronic device. The architecture according to one or more embodiments is expandable from one charger with one USB type-C port coupled to a plurality of battery stacks, to a plurality of chargers with respective USB type-C ports all coupled to a plurality of battery stacks respectively housed in distinct electronic devices.

Abstract: The present embodiments relate generally to DC-DC converters and more particularly to a scheme for providing current sharing between parallel converters in a multiphase configuration. In some embodiments, a cycle-by-cycle instant correction to the compensation signal offset is provided based on the current share error between the paralleled converters so as to achieve improved instant current share performance.

Abstract: The semiconductor device has a wiring M 2, an interlayer insulating film IL3 formed on the wiring M 2, and two wirings M 3 formed on the interlayer insulating film IL3, and the wiring M 3 is connected to the wiring M 2 by a conductor layer PG2 formed in the interlayer insulating film IL3. A recess CC3 is formed on the upper surface IL3a of the interlayer insulating film IL3, and the recess CC3 is defined by a side surface S 31 connected to the upper surface IL3a and a side surface S 32 connected to the side surface S 31, and the side surface S 32 is inclined so that the width WC3 of the recess CC3 decreases in the direction from the upper surface IL3a of the interlayer insulating film IL3 toward the upper surface IL2a of the interlayer insulating film IL2.

Abstract: A semiconductor device includes a first pair of nitride semiconductor regions, and a current confinement region which includes a first portion, a second portion disposed on a side of the first portion, and a third portion disposed on another side of the first portion. A width of the second portion is larger than a width of the first portion, the width of the second portion is larger than a width between the first pair of nitride semiconductor regions, and both ends of the second portion are covered by the first pair of nitride semiconductor regions, respectively.

Abstract: The present disclosure provides a semiconductor device in which shortening of system rise time is achieved. A power supply system conformed to a USBPD standard includes: a plurality of USB ports; a common power supply unit common to the plurality of USB ports; a plurality of power supply units corresponding to the plurality of USB ports, a plurality of controllers corresponding to the plurality of USB ports; and a management unit executing allocation of maximum power to be assigned to the plurality of USB ports in accordance with signals from the plurality of controllers. The management unit determines whether surplus power is generated in maximum power assigned to a first USB port by execution of the allocation of the maximum power and, when surplus power is generated, increases the maximum power assigned to a second USB port.

Abstract: The present embodiments provide a region of a semiconductor device comprising a plurality of power transistor cells configured as trench MOSFETs in a semiconductor substrate. At least one active power transistor cell further includes a trenched source region wherein a trench bottom surface of the trenched source contact is covered with an insulation layer and layer of a conductive material on top of the insulation layer, to function as an integrated pseudo Schottky barrier diode in the active power transistor cell.

Abstract: A spectrometer having a plasmonic filter/microlens arrangement is provided. The spectrometer can include a controller; an image sensor with a pixel array formed by a plurality of pixels coupled to the controller; and an optical layer over the image sensor. The optical layer can include a plasmonic microlens array having a plurality of microlenses positioned over the spacer layer, each microlens of the plasmonic microlens array focusing light on one of the plurality of pixels, and a plasmonic filter array arranged with the plasmonic microlens array such that light incident on each of the plurality of pixels has a transmission function. The microlenses and plasmonic filters can be formed of a composite structure.

Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

Abstract: A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.

Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.