Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.

Abstract: A nitride semiconductor device includes an electron transit layer formed from a nitride semiconductor, an electron supply layer formed on the electron transit layer from a nitride semiconductor having a larger band gap than the electron transit layer, a gate layer formed on the electron supply layer from a nitride semiconductor including an acceptor impurity, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and including first and second openings separated in a first direction, the gate layer being disposed therebetween, a source electrode contacting the electron supply layer through the first opening, a drain electrode contacting the electron supply layer through the second opening, and an auxiliary electrode formed above the electron supply layer, directly covered by the passivation layer, and disposed between the gate electrode and the drain electrode in plan view.

Abstract: A tactile sense presentation device includes: an object information acquisition part configured to acquire, as a state of an object, object information related to at least one selected from the group of a position, a direction, a distance, a speed, an acceleration, and urgency; and a tactile stimulus presentation part configured to present the state of the object as a tactile stimulus in a pseudo manner based on the object information.

Abstract: A semiconductor device includes a switching element including an element obverse surface, leads, bonding layers, and a sealing resin. The switching element includes a first electrode, a second electrode, and a third electrode each formed at the element obverse surface. The leads include a first lead, a second lead, and a third lead. The bonding layers include a first bonding layer bonding the first lead and the first electrode, a second bonding layer bonding the second lead and the second electrode, and a third bonding layer bonding the third lead and the third electrode. The sealing resin includes a resin first surface facing in the same direction as the element obverse surface. The first lead, the second lead and the third lead include a first terminal portion, a second terminal portion and a third terminal portion, respectively, which are exposed at the resin first surface.

Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode, an insulation layer covering the electron supply layer, the gate layer, and the gate electrode and including a first opening and a second opening, a source electrode, and a drain electrode. The source electrode includes a source field plate covering the insulation layer and including an end located between the second opening and the gate layer in plan view. The insulation layer includes a first insulation layer part and a second insulation layer part. The first insulation layer part is disposed on the electron supply layer in contact with the drain electrode and has a first thickness. The second insulation layer part is disposed on the gate electrode in contact with the source field plate and has a second thickness. The second thickness is greater than the first thickness.

Abstract: A semiconductor device includes a semiconductor chip that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor chip and connected to a first potential, a second conductive layer that opposes the first conductive layer of the principal surface in a normal direction and is connected to a second potential higher than the first potential, an insulating layer that is formed between the first conductive layer and the second conductive layer, and a first pad that is formed in a region separated from a region that opposes the second conductive layer in a first direction in a plan view when the semiconductor chip is viewed in the normal direction and that is electrically connected to the first conductive layer.

Abstract: The autonomous movement device includes: an reception unit that is an antenna unit configured to receive output information; an angle estimation unit configured to estimate an arrival direction of the output information; a reception strength determination unit configured to determine a reception strength of the output information in the estimated arrival direction; an operation control unit configured generate movement direction information including a movement direction for moving an autonomous movement device, according to the estimated arrival direction and a magnitude of or a change in the reception strength; and a drive unit configured to generate drive information corresponding to the movement direction information.

Abstract: A MEMS sensor includes a semiconductor chip that has a first principal surface and a second principal surface and that has a cavity, a frame portion that forms a bottom portion and a side portion of the cavity, and a movable portion that is formed on the side of the first principal surface and that is supported by the frame portion in a floating state with respect to the cavity, and, in the MEMS sensor, the frame portion has a stepped surface formed at a height position between the bottom portion of the cavity and the first principal surface, and the movable portion includes a main body portion facing the cavity in a first direction and an extension portion that extends from the main body portion toward an upper region of the stepped surface in a second direction and that faces the stepped surface in the first direction.

Abstract: The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

Abstract: A semiconductor device includes an insulating layer, conductors, a semiconductor element and a sealing resin. The insulating layer has first and second surfaces opposite to each other in the thickness direction. Each conductor has an embedded part whose portion is embedded in the insulating layer and a redistribution part disposed at the second surface and connected to the embedded part. The semiconductor element has electrodes provided near the first surface and connected the embedded parts of the conductors. The semiconductor element is in contact with the first surface. The sealing resin partially covers the semiconductor element and is in contact with the first surface. The redistribution parts include portions outside the semiconductor element as viewed in the thickness direction. The insulating layer has grooves recessed from the second surface in the thickness direction. The redistribution parts are in contact with the grooves.

Abstract: A direct-current voltage is applied to a series circuit composed of a switching transistor, a sense resistor, and a coil. A control circuit is configured to be capable of performing current control in which the control circuit, after turning on the switching transistor, determines a turn-off time point of the switching transistor based on a sense voltage appearing across the sense resistor, and to turn off the switching transistor during the current control if, despite a predetermined time having passed after the switching transistor being turned on, the sense voltage does not reach a predetermined threshold voltage.

Abstract: A method of evaluating a natural frequency of a piezoelectric vibrator including a vibrating membrane and a piezoelectric element, includes: acquiring power-generating wave information of the piezoelectric vibrator from vibration of the vibrating membrane, which is caused by generating an electric field in a piezoelectric film of the piezoelectric element to displace the vibrating membrane and then extinguishing the electric field in a state where the vibrating membrane is displaced; and measuring a period of a power-generating wave based on the power-generating wave information and determining a reciprocal of the period as the natural frequency of the piezoelectric vibrator.

Abstract: A semiconductor device includes: a substrate; a device region provided in the substrate; a terminal covering the device region in a plan view; a plurality of pseudo-bumps densely arranged on the terminal in a state of being opened from a wire; and at least one genuine bump arranged more sparsely than the plurality of the pseudo-bumps on the terminal in a state of being connected to the wire.

Abstract: A semiconductor device includes: a base including a p-type substrate, an n-type semiconductor layer formed on the p-type substrate, and an element region having a transistor provided with a source region and a drain region, which are formed at an interval in a surface layer portion of the n-type semiconductor layer; and a p-type element isolation region formed in a surface layer portion of the base so as to partition the element region, and having an endless shape in a plan view, wherein the n-type semiconductor layer in the element region has a property that an n-type impurity concentration increases stepwise or continuously from a surface of the n-type semiconductor layer toward the p-type substrate over an entire region along a surface of the p-type substrate.

Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Abstract: A fabricating apparatus (2) of an sic epitaxial wafer disclosed herein includes: a growth furnace (100A); a gas mixing preliminary chamber (107) disposed outside the growth furnace and configured to mix carrier gas and/or material gas and to regulate a pressure thereof; a wafer boat (210) configured so that a plurality of SiC wafer pairs (200WP), in which two substrates each having an SiC single crystal in contact with each other in a back-to-back manner, are disposed at equal intervals with a gap therebetween; and a heating unit (101) configured to heat the wafer boat disposed in the growth furnace to an epitaxial growth temperature. The carrier gas and/or the material gas are introduced into the growth furnace after preliminarily being mixed and pressure-regulated in the gas mixing preliminary chamber (107) to grow an SiC layer on a surface of each of the plurality of SiC wafer pairs.

Abstract: A semiconductor device includes a semiconductor element including a transistor, a gate interconnect electrically connected to a gate electrode and extending in a first direction, two connection pads electrically connected to a source or drain electrode and separated in a second direction orthogonal to the first direction in plan view, a passivation layer formed on the gate interconnect, and an organic film layer formed on the passivation layer, a conductive bonding material disposed on the semiconductor element and at least partially overlapping the gate interconnect and the connection pads in plan view, and a conductive member disposed on the conductive bonding material. The connection pads are electrically connected to the conductive member via the conductive bonding material. The gate interconnect is disposed between the connection pads in plan view. The passivation layer is separated from the conductive bonding material by the organic film layer being thicker than the passivation layer.

Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.

Abstract: A semiconductor device includes a chip, a drain region, a source region formed at the surface layer portion of the main surface at a distance from the drain region, a channel inversion region formed on a side of the source region between the drain region and the source region in the surface layer portion of the main surface, a drift region formed in a region between the drain region and the channel inversion region in the surface layer portion of the main surface, a gate insulating film having a first portion that covers the channel inversion region on the main surface and a second portion that covers the drift region on the main surface, and a gate electrode having a first electrode portion covering the first portion and a second electrode portion led out from the first electrode portion onto second portion so as to partially expose second portion.