Patents Assigned to Silicon Graphics, Inc.
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Patent number: 6317134Abstract: A computer system having a shared system memory, and system software in the computer system, are described herein. The computer system has a general purpose, shared system memory that is used for all processing, including video input/output operations, image conversion operations, and rendering operations. In operation, a digital media (DM) Pbuffer is created. The DM Pbuffer is aliased as a DM buffer in the system memory. This is done by storing in a color buffer identifier of the DM Pbuffer an identifier of the DM buffer. Thereafter, all graphical rendering operations directed to the DM Pbuffer are actually performed using the DM buffer.Type: GrantFiled: August 20, 1997Date of Patent: November 13, 2001Assignee: Silicon Graphics, Inc.Inventors: Bent Hagemark, Angela Lai, Kevin Meier, Jonathan Wesener, Brian Beach, John Wiltse Carpenter, Terrence Crane
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Patent number: 6317126Abstract: A method and device for associating a pixel on a surface with one of a plurality of regions defined on the surface. The regions are concentric and defined on the surface by a cutoff angle &phgr; and a transition angle &Dgr;. The concentric regions have a center point that is aligned with a source point disposed above the center point. The source point and the center point form a first axis and the source point and the pixel define a second axis between the source point and the pixel. The method and device determine a difference angle (&phgr;−&Dgr;). The difference angle is then converted into cosine space by determining cos(&phgr;−&Dgr;). Next, the difference angle in the cosine space is converted into a log space. The pixel angle &thgr; between the first axis and the second axis is evaluated in the log and cosine spaces. The region in which the pixel belongs is determined by comparing the difference angle and the pixel angle in one or both of the log space and the cosine space.Type: GrantFiled: March 9, 1999Date of Patent: November 13, 2001Assignee: Silicon Graphics, Inc.Inventor: David C. Tannenbaum
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Patent number: 6317128Abstract: A system and method for providing a graphical user interface (GUI) with anti-interference outlines for enhanced user attention and fluency of work. The GUI utilizes transparency to merge images (or layers) of objects onto a graphical display. For example, variably-transparent (transparent/semi-transparent) or “see through” objects, such as menus, tool palettes, windows, dialogue boxes, or screens are superimposed over similar objects or different background content, such as text, wire-frame or line art images, and solid images. Anti-interference outlines are utilized to heighten the visibility and hence legibility of objects by mitigating visual interference, which is typically the result of overlaying similar colors or luminance values such that one layer “blends” into another.Type: GrantFiled: November 25, 1997Date of Patent: November 13, 2001Assignee: Silicon Graphics, Inc.Inventors: Beverly L. Harrison, William A. S. Buxton, Shumin Zhai
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Patent number: 6317137Abstract: A method, system, and computer program product are provided for multi-threaded texture modulation in axis-aligned volume rendering. Three texture modulation threads are used to modulate texture of three sets of the volumetric data (image sets) in accordance with a texture modulation request. Control is returned from the first texture modulation thread to a main rendering thread while the first texture modulation thread is executing. A user can then interact with a display view while the first texture modulation thread is executing. An intermediate display view of a texture modulated set of volumetric data can be rendered. In one example, a plurality of display connections and contexts are opened for the main rendering thread and each texture modulation thread respectively. Sets of pixel buffers and look-up tables are provided for the respective texture modulation threads. A texture object is included in a context of the main rendering thread.Type: GrantFiled: December 1, 1998Date of Patent: November 13, 2001Assignee: Silicon Graphics, Inc.Inventor: John D. Rosasco
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Patent number: 6314546Abstract: An non-iterative approach for estimating interconnect capacitive effects. The non-iterative approach includes a method for estimating the interconnect capacitive effects. The method includes modeling the gate and estimating an effective capacitance for the interconnect capacitive effects. The effective capacitance estimation includes modeling the gate load at an output of the gate. The gate load modeling includes approximating an admittance of the gate load to a single capacitance model in addition to approximating the admittance of the gate load to a Π model. The gate load modeling also includes matching a gate response for the Π model with the gate response for the single capacitance model to determine the effective capacitance. Another aspect of the method for estimating the interconnect capacitive effects includes modeling the gate using an equivalent circuit, and modeling the load at an output of the gate.Type: GrantFiled: March 26, 1999Date of Patent: November 6, 2001Assignee: Silicon Graphics, Inc.Inventor: Sudhakar Muddu
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Patent number: 6313836Abstract: A computer implemented method of annotating a geometric figure displayed and manipulable in three-dimensional representation on a display of a computer system with a pointer is described. The pointer is also displayed and manipulable in three-dimensional representation on the display. The method associates multimedia functions with the geometric figure. The pointer is positioned to point at an area of the geometric figure using a control device. The geometric figure is displayed in a particular view orientation when the pointer points at the area of the geometric figure. The pointer is then oriented three-dimensionally such that the pointer can point at the area of the geometric figure at a desired angle. The particular view orientation of the geometric figure with the pointer can be preserved such that the particular view orientation of the geometric figure with the pointer can later be retrieved. The pointer can be activated by attaching a marker to the pointer using the control device.Type: GrantFiled: February 14, 1996Date of Patent: November 6, 2001Assignee: Silicon Graphics, Inc.Inventors: Sanford H. Russell, Jr., Douglas S. Dennis, Richard J. Carey
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Patent number: 6308250Abstract: A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector of mask bits to generate an iota vector having a sequence of values. In one form, each value of the iota vector is a sum of a series of the lower order mask bits up to and including the mask bit corresponding to the entry in the iota vector. In another form, each entry in the iota vector is a sum of a series of lower order mask bits but does not include the mask bit corresponding to the particular entry in the iota vector. In order to calculate the iota vector, the multiple processing units of the present invention communicate the mask bits to the other processing units. Advantages of the present invention include the vectorization of software loops having certain data hazards that prevented conventional compilers from vectorizing the software.Type: GrantFiled: June 23, 1998Date of Patent: October 23, 2001Assignee: Silicon Graphics, Inc.Inventor: Peter Michael Klausler
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Patent number: 6307555Abstract: A method for creating a new subdivision surface from one or more prior subdivision surfaces using a computer, the computer having a processor and a memory, includes establishing in the memory a data structure storing data representing the structures of the prior subdivision surfaces, performing Boolean operations upon prior meshes defining the one or more prior subdivision surfaces to form a resulting mesh defining the new subdivision surface, and storing the resulting mesh in the memory.Type: GrantFiled: September 30, 1998Date of Patent: October 23, 2001Assignee: Silicon Graphics, Inc.Inventor: Eugene T. Y. Lee
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Patent number: 6305463Abstract: A cold plate that provides air or liquid cooling for a computer circuit module and has at least one mounting plate with a board mounting surface on one side for carrying a printed circuit board assembly and a cooling surface located on the other side. A cover is disposed parallel to and spaced apart from the mounting plate with a cooling chamber defined between the two. The cooling chamber is divided into a liquid cooled section and an air cooled section. The liquid cooled section has a coolant inlet and outlet and flow channels for directing coolant through the liquid cooled section from inlet to outlet. The air cooled section has an air inlet and outlet and flow channels for directing air through the air cooled section from inlet to outlet. The cold plate is adapted so that it may be installed into a circuit module and provide either liquid cooling or air cooling for the module.Type: GrantFiled: February 22, 1996Date of Patent: October 23, 2001Assignee: Silicon Graphics, Inc.Inventor: Richard B. Salmonson
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Patent number: 6304300Abstract: The present invention provides a method, a device, and a system for performing gamma correction on a set of pixel data based on a gamma correction curve table. The gamma correction curve table includes a specified total number of intensity levels associated with gamma corrected pixel values with one intensity level per pixel value. The method includes partitioning the gamma correction curve table into N segments such that each of the N segments is associated with a set of intensity levels from the specified total number of intensity levels. A plurality of intensity levels is selected for each of the N segments such that significant banding effects are not visible to the human eye between an adjacent pair of the selected intensity levels. The gamma corrected pixel values are stored for each of the N segments such that each of the plurality of selected intensity levels functions as an index to the associated gamma corrected pixel values.Type: GrantFiled: November 12, 1998Date of Patent: October 16, 2001Assignee: Silicon Graphics, Inc.Inventors: David S. Warren, Andrew D. Bowen, David L. Dignam
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Patent number: 6301704Abstract: A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i.e., optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.Type: GrantFiled: June 16, 1998Date of Patent: October 9, 2001Assignee: Silicon Graphics, Inc.Inventors: Frederick Chow, Sun Chan, Peter Dahl, Robert Kennedy, Shin-Ming Liu, Raymond Lo, Mark Streich, Peng Tu
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Patent number: 6301579Abstract: A data structure visualization tool visualizes a data structure such as a decision table classifier. A data file based on a data set of relational data is stored as a relational table, where each row represents an aggregate of all the records for each combination of values of the attributes used. Once loaded into memory, an inducer is used to construct a hierarchy of levels, called a decision table classifier, where each successive level in the hierarchy has two fewer attributes. Besides a column for each attribute, there is a column for the record count (or more generally, sum of record weights), and a column containing a vector of probabilities (each probability gives the proportion of records in each class). Finally, at the top-most level, a single row represents all the data. The decision table classifier is then passed to the visualization tool for display and the decision table classifier is visualized.Type: GrantFiled: October 20, 1998Date of Patent: October 9, 2001Assignee: Silicon Graphics, Inc.Inventor: Barry G. Becker
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Patent number: 6292200Abstract: A computer graphics system having a hyperpipe architecture. Multiple rendering pipes are coupled together through a hyperpipe network scheme. Each of the rendering pipes are capable of rendering primitives for an entire frame or portions thereof. This enables multiple rendering pipes to process graphics data at the same time. A controller coordinates the multiple rendering pipes by sending requests to the appropriate rendering pipes to retrieve the pixel data generated by that particular pipe. It then merges the pixel data received from the various rendering pipes. A single driver then draws the three-dimensional image out for display.Type: GrantFiled: October 23, 1998Date of Patent: September 18, 2001Assignee: Silicon Graphics, Inc.Inventors: Andrew Bowen, Dawn Maxon, Gregory Buchner
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Patent number: 6292192Abstract: A texture procedure allows the rendering of curve bounded objects to a graphics display device directly from a high level curve-based description. The method comprises receiving a curve-based description of the graphics object and dividing the graphics object into a rectangular mesh of texels. Each texel is then detailed by defining a combination of curved geometry functions and a boolean function. These function are then evaluated for each pixel of the graphics display device thereby rendering the graphics object to a graphics display. The texture procedure features include being procedural based and not image-based. This allows a rendering with continued accuracy even under arbitrary magnification conditions. Furthermore, the texture procedure is defined as such that will allow it to function using conventional tri-linear interpolation hardware.Type: GrantFiled: January 9, 1998Date of Patent: September 18, 2001Assignee: Silicon Graphics, Inc.Inventor: Henry Packard Moreton
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Patent number: 6289424Abstract: A memory management and control system that is selectable at the application level by an application programmer is provided. The memory management and control system is based on the use of policy modules. Policy modules are used to specify and control different aspects of memory operations in NUMA computer systems, including how memory is managed for processes running in NUMA computer systems. Preferably, each policy module comprises a plurality of methods that are used to control a variety of memory operations. Such memory operations typically include initial memory placement, memory page size, a migration policy, a replication policy and a paging policy. One method typically contained in policy modules is an initial placement policy. Placement policies may be based on two abstractions of physical memory nodes. These two abstractions are referred to herein as “Memory Locality Domains” (MLDs) and “Memory Locality Domain Sets” (MLDSETs).Type: GrantFiled: September 19, 1997Date of Patent: September 11, 2001Assignee: Silicon Graphics, Inc.Inventor: Luis F. Stevens
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Patent number: 6281108Abstract: A system and method for providing power to the gates of a semiconductor chip routes power and ground from one layer of the chip to another layer of the chip using a first metal strip located at a first metal layer and a second metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer. A stacked via is used to connect the first metal strip to the second metal strip. The stacked via may comprise, for example, a first via connecting the first metal strip to an intermediate metal strip and a second via connecting the intermediate metal strip to the second metal strip. Alternatively, the stacked via may comprise a plurality of vias connecting the first metal strip to the intermediate metal strip and a plurality of vias connecting the intermediate metal strip to the second metal strip.Type: GrantFiled: October 15, 1999Date of Patent: August 28, 2001Assignee: Silicon Graphics, Inc.Inventor: Timothy P. Layman
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Patent number: 6282583Abstract: A matrix processor comprises a system with a variable number of buses, each bus having a variable number of processing elements which may operate in parallel. Each bus accesses a port into a memory crossbar and a multiport memory system also accesses crossbar ports. Efficient sharing of bus accesses by processors and synchronization of processors on each bus is accomplished via registers located on the buses, which may be read and written by processors. Interbus synchronization is also accomplished via register accesses. The matrix processor may be configured as a coprocessor or as a stand alone device. A method of synchronizing the processors and buses, performed by at least one processor on at least one bus, includes reading a barrier state of the processors, synchronizing the processing elements on a each bus, reading the barrier state of the buses, and synchronizing each bus.Type: GrantFiled: June 4, 1991Date of Patent: August 28, 2001Assignee: Silicon Graphics, Inc.Inventors: Philip A. Pincus, Alan E. Charlesworth, Bradley R. Carlile
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Patent number: 6282195Abstract: A switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. The devices are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to several destination ports. Different packets may be transmitted concurrently through the switched router. The packets are comprised of a command word containing information corresponding to packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet.Type: GrantFiled: January 9, 1997Date of Patent: August 28, 2001Assignee: Silicon Graphics, Inc.Inventors: Steven C. Miller, James E. Tornes
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Patent number: 6280257Abstract: The present invention is drawn to a system for attaching and supporting a cable to an IO panel of an electronic component such as the IO back panel of a computer. The system is comprised of a cable dock coupled to an IO panel, with a gasket disposed within the cable dock to form a conducting path from the IO panel to the cable backshell. In particular, a cable dock is fixed to the IO panel where an IO connector is exposed. Once the cable backshell is plugged into the cable dock, the cable dock provides mechanical support for a cable assembly comprising the cable-end connector, the cable backshell and the cable. The cable assembly is secured by the cable dock rather than by the coupling made between the cable-end connector and the IO connector. The cable dock also orients the cable-end connector in coupling to the IO connector such that the cable backshell is prevented from being incorrectly plugged into the cable dock.Type: GrantFiled: January 6, 2000Date of Patent: August 28, 2001Assignee: Silicon Graphics, Inc.Inventors: Dave North, Steve Dean
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Patent number: 6279073Abstract: A configurable synchronizer (10) for DDR-SDRAM (12) is provided that includes a strobe select module (40) operable to receive a memory select signal (106) and to pass strobe signals (20, 30) from one or more DDR-SDRAMs (16, 18) to a number of synchronizer circuits (44) corresponding to data signals (17) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (106). A rising edge latch (174) receives a rising edge data signal (170) and latches the rising edge data signal (170) through the rising edge latch (174) on a rising edge of the strobe signal (152). A falling edge latch (176) receives a falling edge data signal (172) and latches the falling edge data signal (172) through the falling edge latch (176) on a falling edge of the strobe signal (152).Type: GrantFiled: September 30, 1999Date of Patent: August 21, 2001Assignee: Silicon Graphics, Inc.Inventors: David E. McCracken, David L. McCall