Abstract: A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.

Abstract: In a computer system having a plurality of modules connected by a bus, wherein the plurality of modules includes a first module and wherein the system has a word width of two or more bytes, a system and method of byte swapping bytes within a word stored in a location on the first module. An address is constructed, wherein constructing an address includes inserting address bits pointing to the location and activating an attribute bit in the address indicating whether bytes within the word should be swapped. The address is driven on the bus and received at the first module. If the attribute bit is active, byte swapping the word.

Abstract: A cable connector assembly for high frequency applications having reduced electromagnetic emissions. Aspects include providing physical spacing and electrical isolation between the signal conductors and a conductive housing. An isolative member provides reduced capacitive coupling. One embodiment includes spring preloading of the electrical connecter relative to the housing. One embodiment includes a connector floating longitudinally within a conductive housing.

Abstract: There is disclosed apparatus and apparatus for impedance control to provide for controlling the impedance of a communication circuit using an all-digital impedance control circuit wherein one or more control bits are used to tune the output impedance. In one example embodiment, the impedance control circuit is fabricated using circuit components found in a standard macro library of a computer aided design system. According to another example embodiment, there is provided a control for an output driver on an integrated circuit (“IC”) device to provide for forming a resistor divider network with the output driver and a resistor off the IC device so that the divider network produces an output voltage, comparing the output voltage of the divider network with a reference voltage, and adjusting the output impedance of the output driver to attempt to match the output voltage of the divider network and the reference voltage.

Abstract: A method, system, and program product for designing and verifying an electronic circuit. A circuit logic design is translated into a netlist using a synthesis tool. The synthesis tool receives inputs of placing, routing, and timing information. Timing delays in the logic design are represented in the netlist using the placing and routing information. It is determined whether a timing goal has been reached based on the timing delays. When the timing goal has not been reached, changes are made to the placing, routing, and timing information, and the synthesis tool is re-executed using the changed information until the timing goal is reached.

Abstract: A display is capable of displaying images in response to differently formatted signals. The display includes a switch that enables a user to select among a plurality of signal formats. The switch has a first setting that corresponds to a first of the plurality of signal formats and a second setting that corresponds to a second of the plurality of signal formats. The display also includes a memory module that receives requests from a channel and transmits a response associated with the setting of said switch.

Abstract: A system and method for generating a image, where the image comprises both a graphical user interface (GUI) and a subject graphics image. A first graphics pipeline renders the subject graphics image. A second graphics pipeline renders the GUI graphics data. A compositor then composites together the rendered subject graphics data that is produced by the first graphics pipeline, and the rendered GUI graphics data that is produced by the second graphics pipeline.

Abstract: A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and on resistance, and edge rate over a wide range of variations in manufacturing process, operating voltages and temperature.

Abstract: A modular computing system that includes an enclosure, a rack mounted inside the enclosure and a plurality of modular bricks. The modular bricks each include electronic components and are supported by the rack. The computing system further includes a floor tile supporting the enclosure. The floor tile includes a plurality of fans that exchange air with each of the modular bricks to cool the electronic components in each modular brick.

Abstract: A modular computing system that includes an enclosure and a rack at least partially mounted within the enclosure. The modular computing system further includes a plurality of modular bricks that each include electronic components. The modular bricks are mounted in the rack and connected to the conduits in the rack. A fan is also connected to the conduits in the rack such that the rack exchanges air between the fan and each modular brick to cool the electronic components in each of the modular bricks.

Abstract: A modular computing system that includes an enclosure with a rack. A plurality of modular bricks that each include heat-generating electronic components are mounted in the rack. A fan brick that includes at least one fan is also mounted in the rack. The fan brick exchanges air between each modular brick and the fan brick to cool the electronic components in each of the modular bricks.

Abstract: A method, system, and program product for designing an electronic circuit. The electronic circuit has a source component, a sink component and a wire connecting the source and sink components. In one aspect, the wire is divided into wire segments and repeater buffers are added to connect the wire segments. The number of repeater buffers is based on the calculated delay of the global net. In another aspect, the metal routes of the wire are widened to reduce delays on a global net. In these ways, the timing goal of the electronic circuit is met, such that an operation in the electronic circuit will complete within one clock cycle.

Abstract: A novel packet switched routing architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are coupled to a central packet switched router via links. Due to the nature of these tightly coupled links, high data rates can be achieved between devices and the packet switched router with minimal pins. Any device can communicate to any other device via the packet switched router. The packet switched router has the capability of establishing multiple communication paths at the same time. Hence, multiple communications can occur simultaneously, thereby significantly increasing the overall system bandwidth.

Abstract: System, method and apparatus for compressing and decompressing image data. In an embodiment, a color cell is compressed by: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color.

Abstract: Methods, systems, and computer program products for blending textures used to render computer generated images are provided. In an embodiment of the invention, a MIP-mapped mask texture is constructed. Each MIP-level of the MIP-mapped mask texture includes texels representative of different mask information. The MIP-mapped mask texture is sampled during rendering to obtain mask information. The obtained mask information is used to blend between textures. The invention is used to blend, for example, between multiple textures wherein, zero, one, or more of the textures are MIP-mapped and/or between different levels of one or more three-dimensional textures. In an embodiment, the most appropriate texture amongst multiple textures, each providing coverage at different resolutions, is selected for a fragment being rendered, thereby avoiding texture scintillation.

Abstract: A system, method and computer program product for forming an object proxy. In one embodiment, a method forms an object proxy that approximates the geometry of an object. The method includes forming a volume that encompasses the object, forming an isosurface within the volume, adjusting the isosurface relative to a surface of the object, and pruning the isosurface to obtain the object proxy. An apparatus includes an isosurface former that forms an isosurface within a volume encompassing an object, and an isosurface shaper that adjusts the isosurface relative to the surface of the object and prunes the isosurface to obtain the object proxy.

Abstract: A system and method for rendering with an object proxy. In one embodiment, a method includes forming a set of view textures corresponding to a set of viewing directions; selecting a viewing direction for rendering; selecting at least two view textures from the formed set based on the selected viewing direction; and rendering the object proxy at the selected viewing direction. The rendering step includes applying texture from the selected view textures onto the selected object proxy. The view texture set forming step includes: calculating texture coordinates for the object proxy based on the level of obstruction at different portions of the object proxy and texture packing data; and drawing portions of the object based on the level of obstruction data for the object proxy and based on the texture packing data to obtain a view texture at the selected viewing direction.

Abstract: A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the “shared state” that allows reading of the data, but does not permit modifications to the data (i.e., modifications that would have to be written back to memory). If it is desired to modify the data, a directory facility will issue a purge to all caches of the shared-state data for that cache line, and then the processor that wants to modify the data will request an exclusive-state copy to be fetched to its lower-level cache and to all intervening levels of cache.

Abstract: A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal.

Abstract: A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).