Abstract: The present invention is a system that includes a tracking menu that tracks the movement of a position transducer, such as a stylus or a mouse, as the transducer is moved about in association with a display. The menu is typically displayed on top of other objects in the display. The menu includes a tracking symbol, such as an arrow or cursor, positioned corresponding to inputs from the transducer as it is moved by a user. A mobile tracking region is also included. This tracking region has a tracking boundary or edge enclosing the tracking symbol where the tracking symbol is movable within the boundary or hits without the menu moving. The tracking region or entire menu moves in correspondence to the tracking symbol when the tracking symbol encounters the boundary or hits while the symbol is moving. The tracking region also has menu controls or buttons that are activatable when the tracking symbol corresponds to the controls.

Abstract: A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. The scan test interface system and method receives scan test signals, facilitates flexible configuration of scan test signals and transmits scan test signals on subordinate scan test chains. A scan test interface includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: A system, method, and computer program product for creating a sequence of computer graphics frames, using a plurality of rendering pipelines. For each frame, each rendering pipeline receives a subset of the total amount of graphics data for the particular frame. At the completion of a frame, each rendering pipeline sends a performance report to a performance monitor. The performance monitor determines whether or not there was a significant disparity in the time required by the respective rendering pipelines to render their tiles. If a disparity is detected, and if the disparity is determined to be greater than some threshold, an allocation module resizes the tiles for the next frame. This serves to balance the load across rendering pipelines for each frame.

Abstract: The present invention is a system that allows a number of 3D volumetric display or output configurations, such as dome, cubical and cylindrical volumetric displays, to interact with a number of different input configurations, such as a three-dimensional position sensing system having a volume sensing field, a planar position sensing system having a digitizing tablet, and a non-planar position sensing system having a sensing grid formed on a dome. The user interacts via the input configurations, such as by moving a digitizing stylus on the sensing grid formed on the dome enclosure surface. This interaction affects the content of the volumetric display by mapping positions and corresponding vectors of the stylus to a moving cursor within the 3D display space of the volumetric display that is offset from a tip of the stylus along the vector.

Abstract: A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test interface comprising a scan interface chip (SIC) that facilitates a flexibly programmable system level scan test architecture. The SIC includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.

Abstract: A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the “shared state” that allows reading of the data, but does not permit modifications to the data (i.e., modifications that would have to be written back to memory). If it is desired to modify the data, a directory facility will issue a purge to all caches of the shared-state data for that cache line, and then the processor that wants to modify the data will request an exclusive-state copy to be fetched to its lower-level cache and to all intervening levels of cache.

Abstract: The present invention is a system and method that facilitates consistency maintenance and recovery from a system or process crash with valid data. A data consistency maintenance and recovery system and method of the present invention utilizes a dual page configuration and locking process to store and track data associated with multiple indexes of a database. A primary page is utilized as the primary data storage location and a mirror page operates as copy of the primary page except during certain stages of data manipulation (e.g., a write operation). Read operations access information from unlocked primary pages. Write operations access, lock and update a mirror page, then access, lock and update a primary page. Page accesses are tracked (e.g., counted). Then a write process unlocks and syncs the primary page to disk as well as the mirror page. A page with consistent data is copied to a page with inconsistent data during a process system crash recovery.

Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.

Abstract: A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The multi-processor system (10) also includes an external switch (14) coupled to each of the plurality of processors (12). The external switch (14) passes data to and from any of the plurality of processors (12). The external switch (14) has an external directory (22). The external directory (22) provides a memory reference for each of the plurality of processors (12) to remote data that is not provided within its own integrated memory directory (18).

Abstract: A system that combines a radial marking menu portion with a linear menu portion in a single menu display. Item selection in the linear portion is performed by location selection using a pointing device. Item selection in the marker portion is determined by the pattern of a stroke made by the pointing device with the system ignoring linear menu items across which the stroke completely passes.

Abstract: An information capturing device (10) includes a controller (12) and a memory (14). The controller (12) partitions a memory space of the memory (14) into a plurality of memory blocks (20). The controller (12) controls the storage of received information into a first set (22) of the plurality of memory blocks (20). The controller (12) continues to store received information only in the first set (22) of the plurality of memory blocks (20) through reuse and recycle until a first triggering event occurs. In response to the first triggering event, the controller (12) halts the storage of received information in the first set (22) of the plurality of memory blocks (20) and begins storing received information in a second set (24) of the plurality of memory blocks (20). When the second set (24) of the plurality of memory blocks (24) has reached its storage capacity, the controller (12) begins storing received information in a third set (26) of the plurality of memory blocks (20).

Abstract: Noise estimation for coupled interconnects in deep submicron integrated circuits. One aspect of the invention is a method for interconnect coupling noise estimation. Another aspect of the invention is a computer readable medium embodying computer program code. The computer program code is configured to cause a computer to perform steps for estimating the interconnect coupling noise. The interconnect coupling noise estimation (hereafter noise estimation) includes modeling a circuit. The circuit includes a pair of interconnects, each interconnect connecting a driver gate to a load gate, where signal activity at a first interconnect of the pair of interconnects is having an impact on a second interconnect of the pair of interconnects. The circuit modeling includes modeling the first and second interconnects, driver gates, and load gates. Driver gates are modeled using a voltage source driving a resistance. Load gates are modeled using a capacitance.

Abstract: Methods and systems for animating with proxy surfaces are provided. A method for animating includes preprocessing an object to form proxy surfaces of part(s) and/or joint(s), and rendering the proxy surfaces to be animated. In an embodiment, preprocessing includes dividing an object to be animated into parts that can move independently without changing shape, forming a proxy surface for each of the parts corresponding to an initial viewing direction, and obtaining a set of view textures for each of the proxy surfaces. Each part proxy surface is then rendered at a new viewing direction. The new viewing direction is function of an object transformation, part transformation, and an initial viewing direction. The object is then animated by repeating the rendering steps. In another embodiment, the object to be animated is divided into parts and at least one joint that can change shape.

Abstract: A system and method for resource recovery in a distributed system uses a resource audit service to monitor the status of a client that receives a resource from a service that allocates the resource. The allocating service registers a callback with the resource audit service identifying the client. The resource audit service subsequently monitors the status of the client. When the resource audit service determines that the client has failed, the resource audit service performs the callback to the allocating service indicating the failure of the client. Upon receiving the callback, the allocating service is able to recover the resource from the client.

Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.

Abstract: A system for approximating a least recently used (LRU) algorithm for memory replacement in a cache memory. In one system example, the cache memory comprises memory blocks allocated into sets of N memory blocks. The N memory blocks are allocated as M super-ways of N/M memory blocks where N is greater than M. An index identifies the set of N memory blocks. A super-way hit/replacement tracking state machine tracks hits and replacements to each super-way and maintains state corresponding to an order of hits and replacements for each super-way where the super-ways are ordered from the MRU to the LRU. Storage for the state bits is associated with each index entry where the state bits include code bits associated with a memory block to be replaced within a LRU super-way. LRU logic is coupled to the super-way hit/replacement tracking state machine to select an LRU super-way as a function of the super-way hit and replacement history.

Abstract: A system for repairing a memory column includes a multiplexer operable to receive a first data bit and a second data bit. The multiplexer is operable to select one of the first data bit and the second data bit. The system also includes a control generator operable to receive a control signal indicating an error in the first data bit. The control generator is operable to generate a select signal, and the multiplexer is operable to select the second data bit in response to the select signal.

Abstract: The present invention provides a system and method that facilitates data consistency maintenance between two segments of memory. A data consistency maintenance and recovery system and method of the present invention uses a dual page configuration and locking process to store and track data. A primary page is used as the primary data storage location and a mirror page operates as a copy of the primary page, except during certain stages of data manipulation operations. In one embodiment the present invention facilitates consistency maintenance during a write operation to a database. The present invention also facilitates data recovery following a system or process crash.

Abstract: A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the shared line of memory. An invalidation message is transmitted to each processor in the superset of processors. The number Na of alias processors in the superset of processors is determined and a superacknowledgement message is provided that is equivalent to acknowledging receipt of Na invalidation messages.

Abstract: A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to each job.