Abstract: A method of modeling complex surface models using a network of intersecting non-uniform rational B-spline curves. Topological information of the curve network and interpolating surfaces to the network of curves are automatically generated. Different levels of continuity between surface patches are enforced. Surface patches of three and four sides and positional, tangent or curvature continuity between the patches are provided. Using a constrained minimization process, arbitrary, non-uniform B-spline curves may be used to manipulate the shape of the surfaces interpolating the curve network without violating the continuity conditions enforced during the generation of the surface patches allowing for very complex three-dimensional shapes to be modeled using the method.

Abstract: A method of converting a subdivision surface to a NURBS representation. Adjacent faces of a subdivision surface are merged into a quadrilateral region, and vertices of the rectangular regions are used to generate a NURBS surface. The merging of faces reduces the number of vertices needed. Faces should not be merged if they do not comprise a quadrilateral region; if they cross an extraordinary point; if they cross a crease; or a face has already been merged. Imaginary vertices can be generated if not enough vertices are present for a face in the subdivision surface to create a corresponding NURBS patch for that face.

Abstract: A cache coherence system and method for use in a multiprocessor computer system having a plurality of processor nodes, a memory and an interconnect network connecting the plurality of processor nodes to the memory. Each processor node includes one or more processors. The memory includes a plurality of lines and a cache coherence directory structure having a plurality of directory structure entries. Each of the directory structure entries is associated with one of the plurality of lines and each directory structure entry includes processor pointer information, expressed as a set of bit vectors, indicating the processors that have cached copies of lines in memory. Processor pointer information may be a function of a processor number assigned to each processor; the processor number may be expressed as a function of a first set of bits and a second set of bits which are respectively mapped into first and second bit vectors of the n bit vectors.

Abstract: An integrated circuit (10) includes a central processing unit (12), an instruction cache (14), a data cache, (16), and a trace recorder. The central processing unit (12) interacts with the instruction cache (14) and the data cache (16) in order to execute instructions. Profile information passed between the central processing unit (12), the instruction cache (14), and the data cache (16) not normally available for external analysis may be captured by the trace recorder (20) in response to various execution points in a program being executed by the central processing unit (12). The profile information captured by the trace recorder (20) may subsequently be provided to external analysis equipment in order to analyze the operation of the central processing unit (12) for study of program execution.

Abstract: A memory system is disclosed that includes memory modules that are longer and taller than conventional prior art memory modules. Each memory module includes two roughly L-shaped openings that extend from the top surface of the memory module near each side surface of the memory module. These L-shaped openings form tabs that extend horizontally along the top surface of the memory module. A guide assembly that includes sockets and guides is adapted to receive the memory module. Rotating latches that couple to each guide near the top of each guide engage a notch on each side surface of the memory module for facilitating insertion and removal. Rotation of each latch into a latched position engages a tab on the memory module so as to securely latch the memory module in place.

Abstract: A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. The system also includes an efficient return channel to minimizine the amount of data transfer bandwidth required in returning status information on the FIFO buffer of the input/output unit.

Abstract: A system for improving the speed of operation of an integrated circuit incorporating long lines includes a first voltage operable to provide power to the circuit. The system also includes a second voltage that is less than the first voltage and a third voltage that is less than the second voltage. The system also includes a node, wherein a first status is indicated when the voltage at the node is the second voltage and a second status is indicated when the voltage at the node is the third voltage. The system also includes an input of a switching element connected to the node wherein the switching element is operable to switch upon the voltage at the node changing between the second voltage and the third voltage.

Abstract: A system that combines a radial marking menu portion with a linear menu portion in a single menu display. Item selection in the linear portion is performed by location selection using a pointing device. Item selection in the marker portion is determined by the pattern of a stroke made by the pointing device with the system ignoring linear menu items across which the stroke completely passes.

Abstract: A computer system (10) can prepare and present on a display (22) a two-dimensional image that includes a perspective view, from a selected eyepoint (71, 152), of an object (23) which is a three-dimensional object of an approximately spherical shape, such as the earth. The system maintains image information for the object at each of several different resolution levels, portions of which are selected and mapped into the perspective view for respective portions of the surface of the object. In order to determine what resolution level to use for a given section of the surface of the object, the system relies on a combination of a logarithm of the square of a distance from the eyepoint to a point on the surface section, and a logarithm of the square of the degree of tilt of the surface section in relation to the eyepoint.

Abstract: A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal.

Abstract: The present invention is directed to a method and a system for maintaining cache coherence in a distributed shared memory (DSM) multiprocessor system. The method begins with a receiving of a shared access request by a receiving node, where the receiving node is an arbitrary node having at least one main memory unit containing information desired to be accessed. Then, the method determines whether the shared access request originates from a local node or from a remote node. When the shared access request originates from a local node, the shared access request is processed as a shared access request. If the shared access request is granted, a sharing vector is generated or updated to reflect the sharing local node(s). When the shared access request originates from a remote node, the shared access request is converted to an exclusive access request and the sharing vector is replaced with a pointer to the requesting remote node. This limits the potential size of the sharing vector according to the local nodes.

Abstract: A system and method are described herein for controlling the white balance and providing gamma correction without compromising gray-scale dynamic range in a flat panel liquid crystal display (LCD). According to one embodiment of the present invention, the flat panel LCD includes electronic circuitry for coupling to a host computer to receive a white-balance adjustment control signal, and electronic circuitry for receiving image data to be rendered on the flat panel LCD. Further, the flat panel LCD of one embodiment is configured for coupling to a color-sensing device to receive optical characteristics data of the flat panel LCD detected by the color-sensing device. The white balance adjustment mechanisms include the provision of two or more light sources of differing color temperature, whose brightness can be independently varied (and distributed through a light distribution mechanism) to adjust color temperature without altering the grayscale resolution of the RGB colors.

Abstract: Switches are used to serially isolate connectors for peripheral devices on a bus. Bus speed is selected based on the number of peripheral devices coupled to the bus via the connectors. Switches are used in the bus to provide selected isolation of the connectors. In one embodiment, the bus is able to operate at higher speeds when fewer connectors are on the bus. A method of configuring the bus determines how many devices are coupled to connectors on the bus. Portions of the bus not having devices coupled to connectors are isolated by controlling the switches between on and off states.

Abstract: A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a virtual address specified in the PTC instruction from the processor's translation lookaside buffer. By purging the virtual address, the memory is deallocated.

Abstract: Translation of PCI level interrupts into packet based messages for edge event drive microprocessors includes, a bridge device receiving interrupts via an interrupt line from one or more PCI devices. The bridge device further sends an interrupt write packet to a CPU to launch the interrupt routine. The interrupt routine services the interrupt and the PCI device negates the interrupt line. At this point, the CPU generates a non-blocking write. This write causes the bridge to check the level of the PCI interrupt line. If the line is active with the interrupt, another write packet is sent, otherwise the interrupt line is negated and the blocking write is ignored. As a result, the present invention prevents an interrupt from a PCI device from being overlooked, from being missed, or from repeating the interrupt by a microprocessor.

Abstract: The present invention is a system that allows a number of 3D volumetric display or output configurations, such as dome, cubical and cylindrical volumetric displays, to interact with a number of different input configurations, such as a three-dimensional position sensing system having a volume sensing field, a planar position sensing system having a digitizing tablet, and a non-planar position sensing system having a sensing grid formed on a dome. The user interacts via the input configurations, such as by moving a digitizing stylus on the sensing grid formed on the dome enclosure surface. This interaction affects the content of the volumetric display by mapping positions and corresponding vectors of the stylus to a moving cursor within the 3D display space of the volumetric display that is offset from a tip of the stylus along the vector.

Abstract: The present invention is a widget display system for a volumetric or true three-dimensional (3D) display that provides a volumetric or omni-viewable widget that can be viewed and interacted with from any location around the volumetric display. The widget can be viewed from any location by duplicating the widget such that all locations around the display are within the viewing range of the widget. A widget can be provided with multiple viewing surfaces or faces making the widget omni-directional. A widget can be continuously rotated to face all of the possible locations of users over a period of time. User locations can be determined and the widget can be oriented to face the users when selected.

Abstract: The present invention is a system that creates a volumetric display and a user controllable volumetric pointer within the volumetric display. The user can point by aiming a beam which is vector, planar or tangent based, positioning a device in three-dimensions in association with the display, touching a digitizing surface of the display enclosure or otherwise inputting position coordinates. The cursor can take a number of different forms including a ray, a point, a volume and a plane. The ray can include a ring, a bead, a segmented wand, a cone and a cylinder. The user designates an input position and the system maps the input position to a 3D cursor position within the volumetric display. The system also determines whether any object has been designated by the cursor by determining whether the object is within a region of influence of the cursor. The system also performs any function activated in association with the designation.

Abstract: An scalable multi-reader/single-writer lock implementation that eliminates contention for lock data structures that can occur in large symmetric multi-processing (SMP) computer systems. The present invention includes a registry head data structure for each critical resource within the computer system. Linked to each of the registry head data structures are one or more client data structures that represent each client (i.e., process, thread, interrupt handler, and the like) that needs read and/or write access to the critical resource represented by the registry head data structure. Further, five operations—Initialization, Adding a Client, Deleting a Client, Obtaining Read Access, and Obtaining Write Access—are provided in order to achieve the goal of contention elimination.

Abstract: Diagnostic environments designed for ccNUMA computing systems require different capabilities than conventional diagnostic programs. Since most conventional operating systems do not permit sufficient access to hardware by application programs, a diagnostic microkernal is distributed to all of the processors of all of the nodes of the computing system. Instead of dumping output to a user interface, diagnostic programs executing under control of the diagnostic microkernal store formatted data in shared memory. A shell process executing at an interface node is notified of errors and informs the user who selects the formatted data in shared memory to be accessed by the shell process for output via a user interface by little more than echoing the data. Either a dumb terminal or a desktop computer or workstation which adds further formatting capabilities may be used for display of the data.