Abstract: A method and apparatus for modeling three-dimensional solid objects are provided. The method of the present invention uses the concept of volumetric objects. Each volumetric object is a decoupled combination of volumetric geometry and volumetric appearance. To be rendered, one or more volumetric objects are tessellated into a series of one or more volumetric primitives. The volumetric primitives are then polygonized. The result is a list of two-dimensional polygons. The list of polygons is then depth sorted, colored, shaded and texture-mapped with the voxel data that forms the basis for the volumetric object. The polygons are composited together in the frame buffer, or other device, to form the final displayable image.

Abstract: A system, method and computer program product is provided for interactive user navigation in a real-time 3D simulation. An assembly builder permits a user to build customized physics-based assemblies for user navigation in a variety of virtual environments. These assemblies are stored in a library and are then accessed by a navigation run-time module that runs in conjunction with, or as a part of, a visual run-time application. The navigation run-time module receives high-level user goal requests via a simple and intuitive user interface, converts them into a series of tasks, and then selects the appropriate assembly or assemblies to perform each task. As a result, complex navigation may be achieved. Once selected, an assembly provides a physics-based eye-point model for user navigation. Collisions between the assembly and objects in the simulation are resolved using a real-time physics engine, thus ensuring smooth, cinematic-style eye-point modeling in addition to real-time control.

Abstract: A system and method thereof for monitoring elapsed time for a transaction. A computer system executes an application to initiate a transaction. An input/output device communicatively coupled to the computer system receives the transaction from the computer system. The input/output device is adapted to have a timer for measuring time until, for example, a response to the transaction is generated. The input/output device monitors the timer to identify when a time period allotted for the response to the transaction is exceeded (e.g., a timeout condition). The input/output device generates a signal to indicate the timeout condition.

Abstract: A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set. The richly featured high performance low cost system is intended to give consumers the change to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.

Abstract: A method and computer program product are presented for converting an arbitrary mesh to a subdivision surface. Where the subdivision surface is to have an odd degree d=2m+1 on the regular part of the mesh, the method includes the steps of subdividing the mesh in a linear fashion, then iteratively smoothing the subdivided mesh m times. Where the subdivision surface is to have an even degree d=2m on the regular part of the mesh, the method includes the steps of subdividing the mesh, calculating the dual of the subdivided mesh, and iteratively smoothing the dual m−1 times. In either case, the resulting subdivision surfaces generalize uniform tensor product B-spline surfaces of any degree to meshes of arbitrary topology. The method uses subdivision rules that involve direct neighbors.

Abstract: A level of detail shading function is produced and stored in a computer readable memory. The level of detail shading function is produced by receiving a shading function, identifying in the shading function at least one candidate block of code for simplification, and generating, for each candidate block of code, at least one simplified block of code that can be substituted for the candidate block of code during image rendering. Candidate blocks of code and simplified blocks of code according to the invention are associated with at least one input parameter and assembled to form the level of detail shading function. During the rendering of an object, input parameters are provided to the level of detail shading function. These input parameters are associated with one or more blocks of code in the level of detail shading function. The input parameters specify how the object is to be shaded using the level of detail shading function.

Abstract: A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and identities of processors (16) affected by the invalidation request to the local block unit (28). The local block unit (28) determines which ones of the identified processors (16) are present in the computer system (10) and generates an invalidation message for each present processor (16) for transfer thereto. Each of the present processors (16) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit (24) that generated the invalidation request.

Abstract: A system and method for high-speed execution of graphics application programs, including shading language instructions, that utilize 3D graphics hardware. The method involves expressing a graphics computation in a platform-independent procedural shading expression, converting the expression (i.e., user application program) into an intermediate representation such as a tree, and then translating it into a sequence of parametric shading expressions. The method can alternatively processes the intermediate tree representation using a cost-based, tree-grammar recognizer such as iburg. The result is a platform-specific and least-cost, in terms of the underlying hardware, sequence of parametric shading expressions that realizes the graphics computation. The system and method is useful in translating platform-independent RenderMan™ Shading Language programs into fast-executing, platform-specific OpenGL™ or Direct3D™ executable code.

Abstract: A ground bracket and method for grounding an electronic device to a structure such as a rail, rack or cabinet. According to one aspect of the invention the ground bracket has a first conductive surface for use in coupling the bracket to the structure and an arcuate portion conductively coupled to the first conductive surface for contacting an electronic device. In another embodiment, a bracket includes a first surface for coupling to a rack, and a portion positioned proximal a computer component that includes a rotatable fastening mechanism for coupling to the computer component.

Abstract: A method and computer program product, within an optimizing compiler, for the global minimization of sign-extension and zero-extension operations in generated code during compilation. The method and computer program product allows, for example, 64-bit compilers targeting the Intel IA64 architecture to improve their SPECint benchmarks by reducing the number of sign-extension and zero-extension operations in the global and intra-procedural scope, thus, speeding up the execution of the compiled program.

Abstract: The present invention is directed to a method and system for sharing a data memory among a plurality of processors in a computer system. In the system and method of the present invention, a plurality of processors are coupled to a data memory for accessing the data memory in N-bit bandwidth. The present invention receives an active signal for accessing the data memory from the plurality of processors. A processor requesting accessing to the data memory asserts an active signal. Among the processors asserting active signals, a processor is selected as a memory master to the data memory. The present invention then transfers the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock cycle. Only one processor is allowed access to the data memory during a given time slot. In the preferred embodiment of the present invention, the N-bit bandwidth is large enough to accommodate the data requirements of all the processors.

Abstract: A compiler for compiling source code whereby the compiled source code is optimized by performing outer loop unrolling (a generalization of “unroll and jam” on selected loop nests. The present invention allows any arbitrarily deep loop nests with non-varying loop bounds to be properly unrolled even in the presence of imperfectly nested code. This is accomplished for two-deep loop nests by transforming the code into multiple adjacent loop nests. In the transformed code, the imperfect code is isolated so that one of the adjacent loops nests has none, and thus can be unrolled and jammed. For three-deep or greater loop nests, the process is repeated recursively from the outer-most loop. The present invention also allows outer loop unrolling for two-deep loop nests with convex bounds, even with the presence of imperfectly nested code. This is accomplished by identifying strips of code which do not contain imperfectly nested code. An unroll and jam operation is executed for the identified strips.

Abstract: A node controller (12) includes a processor interface unit (24) that receives an interrupt signal (50). The processor interface unit (24) includes a register (52) with a forward enable bit (54). In response to the forward enable bit (54) being set, the processor interface unit (24) generates a forward interrupt signal (56) for transfer to an input/output interface unit (26) of the node controller (12). The input/output interface unit (26) generates an interrupt request for transfer to a remote node controller. The input/output interface unit (26) includes an interrupt destination register (58) that includes an identity of a particular remote node controller and associated processor interface unit to which the interrupt request is to be transferred. The remote node controller having a processor attached thereto to handle the interrupt request.

Abstract: A method and system for updating the colorimetric characteristics of a flat panel display over the display's entire lifetime. An advantage of the present invention is that the useful life and the color accuracy of a flat panel display can be extended. In one embodiment of the invention, an initial set of luminance data of a flat panel monitor is programmed into addressable memory locations within that monitor. Thereafter, the luminance output of the lamps of the flat panel monitor is tracked with luminance or colorimetric measuring devices. According to the present invention, the luminance data are used in determining the correlation between voltage settings of the lamps and the color characteristics of the display such as color temperature. By measuring the luminance of the display periodically, a precise and accurate color profile of the flat panel display can be maintained.

Abstract: A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a color television set. The richly featured high performance low cost system is intended to give consumers the chance to interact in real time right inside magnificent virtual 3D worlds to provide a high degree of image realism, excitement and flexibility. An optimum feature set/architecture (including a custom designed graphics/audio coprocessor) provides high quality fast moving 3D images and digital stereo sound for video game play and other graphics applications.

Abstract: New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion.

Abstract: A modular, scalable high-bandwidth computer architecture. A single integrated router/bridge ASIC defines a family of peripheral controllers that accept high-speed packet switched data, either for routing to other, identical controllers, or for routing to on-board PCI buses, or a combination of the two destinations, depending on the number of ASICs employed and their selectable configuration.

Abstract: A method for parameterizing a subdivision mesh in a computer system, the subdivision mesh comprising at least two faces, at least two faces sharing an edge, includes assigning a unique index for each of the at least two faces, assigning, for each of the at least two faces, a first (u) and a second (v) parameter to uniquely parameterize each point on a respective face, each respective u and v parameters for a respective face also being assigned the unique index for that respective face; and at a vertex shared by two faces sharing an edge, setting a first bound for each of the u and v parameters for each of the two faces, and for each of the same two faces, at a vertex not shared by the two faces, setting a second bound for each of the u and v parameters.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.