Abstract: A method and apparatus for providing efficient and accurate electronic data transmission of information on a data bus in the presence of noise. Data signals are received on a plurality of input lines by a spacial derivative encoder. The spacial derivative encoder encodes the signals and transmits them to a receiver having a spacial derivative decoder. The spacial derivative decoder then decodes the signals. Minimal overhead is required as for n input lines only n+1 lines are needed to transmit each of the encoded signals.

Abstract: A system and method for determining a repeater allocation region is disclosed. A path delay equation describing a path delay from a driver to a gate is formulated. A delay constraint is applied to the path delay equation. A repeater allocation region indicating a position of a repeater is determined from the path delay equation.

Abstract: The present invention is a system that allows a user to paint surface related attributes just like texture is painted. The painting actions are in the form of scripts that the user can provide and which are interpreted during painting.

Abstract: A node controller (12) includes a processor interface unit (24), a crossbar unit (26), and a memory directory interface unit (22). Request and reply messages pass from the processor interface unit (24) to the crossbar unit (26) through a processor interface output queue (52). The processor interface unit (24) writes a request message into the processor interface output queue (52) using a processor interface clock to latch a write address from a write address latch (62) in a synchronizer (60). The write address is encoded by a Gray code counter (64) and latched by a first sync latch (66) and a second sync latch (18) using a core clock of the crossbar unit (30). The output of the second sync latch (68) provides one of the inputs to a read address latch (70) using the core clock of the crossbar unit (30).

Abstract: A method for implementing edge blending between a first and second video frame to create a seamless multichannel display system. The method is implemented in a graphics computer system including a processor coupled to a memory via a bus. Within the computer system, a first video frame is rendered for display on a first video channel. A second video frame is rendered for display on a second channel. A first overlap region is rendered onto the first frame to obtain a first blended video frame. A second overlap region is blended onto the second frame to obtain a second blended video frame. The first blended video frame from the first channel and the second blended video frame from the second channel are then combined such that the first overlap region and the second overlap region correspond, thereby forming a seamless junction between the first blended frame and the second blended frame and implementing a high fidelity multichannel display.

Abstract: A structure and method thereof for providing an electrically conductive path between a first conductive point and a second conductive point. The structure includes an insulating material disposed between the first conductive point and the second conductive point. A dipole material is distributed within the insulating material. The dipole material is comprised of randomly oriented magnetic particles. The magnetic particles in a selected localized region of the insulating material are aligned to form an electrically conductive path between the first conductive point and the second conductive point through the insulating material.

Abstract: A system for color balancing within a liquid crystal flat panel display unit. The present invention includes a method and system for altering the brightness of two or more light sources, having differing color temperatures, thereby providing color balancing of a liquid crystal display (LCD) unit within a given color temperature range. The embodiments operate for both edge and backlighting systems. In an embodiment, two planar light pipes are positioned, a first over a second, with an air gap between. The first light pipe is optically coupled to receive light from a first light source having a color temperature above the predetermined range and the second light pipe is optically coupled to receive light from a second light source having a color temperature below the predetermined range.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: A system and method for calculating interconnect response and delay are disclosed. The admittance of the nodes of an interconnect is determined from the attributes of the nodes. Weighted admittance of the nodes are determined from the admittance, and transfer function coefficients are determined the weighted admittance. A transfer function is determined from the transfer function coefficients, and is used to calculate an interconnect delay.

Abstract: A data synchronizer (60) receives a data ready signal (40) at a selector (82). The selector (82) selects either the data ready signal (40) or a delayed version of the data ready signal (40) in response to a speed select signal (88) determined according to a clock speed of a receive core clock (52). The selector (82) provides a select signal (92) to a first latch unit (94) and a second latch unit (96). The first latch unit (94) generates a latched select signal (A) that is provided as a receive data valid signal (48) by a signal generator (108) in response to a slow clock rate for the receive core clock (52). The second latch unit (96) generates a delayed select signal (B) that is used by the signal generator (108) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal (48) in response to a fast clock rate for the receive core clock (52).

Abstract: An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation.

Abstract: Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to occupy minimal printed circuit board surface area so as not to displace electronic components. In another embodiment, an elongated truss-like stiffener is provided that is adapted to be fastened to one side of the printed circuit board and adapted to span the printed circuit board. The elongated stiffener is adapted to have an open structure to minimize cooling flow disturbance and weight. The elongated stiffener includes a plurality of legs forming a truss-like structure.

Abstract: The present invention is a system that produces a position of a rigid object, such as a button, on a deformed model, such as an animated piece of cloth, at each cycle in an animation of the model by isotropically finding a linear approximation of the deformation at the model and finding a rotation of the object allowing attachment of the object to the model. The system removes shear and scaling from a linear transformation of an average deformation of the model. A volumetric area of the deformed model in which the object will reside and which is used for the position determination is specified essentially as a mapping of the object onto the model. The average deformation of the area is calculated and the linear transformation of the object is performed with the average deformation. In finding the rotation a rotation characteristic matrix is created and Eigen vectors or directions are extracted and correspond to the rotation.

Abstract: Apparatus, methods, data structures, and systems are provided for subdividing input data associated with a first software program into job quanta, wherein each job quantum is operable to be executed by a separate software program residing on a different processing element from the first software program. The first software program and the separate software program execute substantially in parallel and output data associated with the executions of the programs are assembled into a single coherent presentation or results data. Moreover, the software programs may be threaded or non-threaded.

Abstract: A system that includes a pop-up graphical user interface that includes menu bars overlapping marking menu zones. The interface pops up at the current position of the cursor when the space bar is held down. The menu bars are positioned around a central marking zone with the common menu bars located above the central zone and task specific menu bars located below the central zone. The common application menu bar is positioned outer most and the common window menu bar is located inner most. The menu bars are sized in a “stair-step” pattern and the commands therein are left and right justified to fill the menu bar evenly. The menu bar menu items are accessed just like menu bar items typically found at the top of windows. The menu bars mimic the menu bars that a user may need to use during tasks that users typically perform using the menu bars found in application windows.

Abstract: A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.

Abstract: A distributed shared memory multiprocessor computer system is provided, which has a number of processors and is divided into partitions. Each partition has within it one or more of the processors, and may also have memory or cache and other related hardware. Although each partition works together and communicates with other partitions to share computational load, the partitions each are independently operable and execute an independent copy of the operating system. The partitions comprise additional features to enable removal of a partition from the operating computer system, and to enable insertion of hardware into the operating computer system.

Abstract: An improved support bracket for supporting electronic devices provides improved adjustability and alignment. The support bracket includes a front surface and a rear surface each including a portion having at least one threaded hole and a support portion between the front surface and rear surface for supporting an electronic device. The support bracket includes a side portion having a mechanism for coupling the side portion to a structure, a guide portion and a support portion for supporting an electronic device.

Abstract: Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to occupy minimal printed circuit board surface area so as not to displace electronic components. In another embodiment, an elongated truss-like stiffener is provided that is adapted to be fastened to one side of the printed circuit board and adapted to span the printed circuit board. The elongated stiffener is adapted to have an open structure to minimize cooling flow disturbance and weight. The elongated stiffener includes a plurality of legs forming a truss-like structure.

Abstract: A cache for AGP based computer systems is provided. The graphics cache is included as part of a memory bridge between a processor, a system memory and a graphics processor. A cache controller within the memory bridge detects requests by the processor to store graphics data in the system memory. The cache controller stores the data for these requests in the graphics cache and in the system memory. The cache controller searches the graphics cache each time it receives a request from the graphics controller. If the a cache hit occurs, the cache controller returns the data stored in the graphics cache. Otherwise the request is performed using the system memory. In this way the graphics cache reduces the traffic between the system memory and the memory bridge, overcoming an important performance bottleneck for many graphics systems.