Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of an access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.

Abstract: A method of a flash memory controller includes: using a processor to issue and generate a command signal into a control logic circuit though a bus; buffering the command signal in a specific queue of a specific channel controller of the I/O circuit; and using the arbitrator to control the specific buffer storing a first transmission history information of the specific communication interface.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for data access in response to a host discard command. The method includes: allocating space in a random access memory (RAM) for an expanded discard table; receiving the host discard command from a host side; appending new entries each including one first logical address to the expanded discard table; and setting a start-address register and/or an end-address register in a performance engine for redefining an address range in the RAM that stores the expanded discard table, thereby enabling the performance engine to search the expanded discard table in the address range in the RAM for determining whether a specific logical address of user data is no longer used.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) to include: simulating to issue a first Joint Test Action Group (JTAG) command through a General-Purpose Input/Output (GPIO) interface (I/F) to the SSD device for stopping a running of a processing unit of a flash controller in the SSD device; simulating to issue a second JTAG command through the GPIO I/F to the SSD device for forcing the SSD device to exit a sleep mode; and simulating to issue a third JTAG command through the GPIO I/F to the SSD device for reading a designated length of data from a static random access memory (SRAM) in the SSD device.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: A method for performing table management of a memory device in predetermined communications architecture with aid of flexible table page grouping and associated apparatus are provided. The method may include: utilizing the memory controller to perform a table management procedure to manage at least one table regarding internal management of the memory device. For example, the table management procedure may include: in response to updating a first previous table content of a first table among the at least one table being needed, writing a first updated table content of the first table into at least one first updated table page of at least one table block; and writing a first RAID parity of the first updated table content into a first parity page, wherein a first updated table page count of the at least one first updated table page protected by the first parity page is determined in real time.

Abstract: The present invention provides a control method of a flash memory controller is disclosed, wherein the flash memory controller is configured to access a flash memory module, and the control method comprising: allocating a memory space within a memory for storing data from the host device; dividing the memory space into a plurality of zone buffers, wherein each of the zone buffers is used to store data corresponding to one zone having an opened state; and for a first zone buffer of the plurality of zone buffers, controlling a first buffer and a second buffer within the first zone buffer to alternately store data of a first zone from the host device and write the data of the first zone to a zoned namespace of the flash memory module.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprising: receiving a settling command from a host device; in response to the settling command, configuring at least one portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically comprises a plurality of zones; generating parameter information according to a configuration of the zoned namespace; and transmitting the parameter information to the host device, for the host device uses the parameter information to set the zone.

Abstract: A data storage device includes a memory device and a memory controller. The memory device has a corresponding total storage capacity and includes multiple memory blocks. The total storage capacity is set to a maximum storage capacity provided by the memory blocks by default. The memory blocks include one or more predetermined memory blocks configured as a buffer to receive data from a host device. The memory controller is coupled to the memory device to access the memory device. In response to setting of a maximum amount of write data, the memory controller determines a value of the total storage capacity according to the maximum amount of write data, and determines a number of said one or more predetermined memory blocks according to the value of the total storage capacity and the maximum storage capacity.

Abstract: A method for reading data from a flash memory is provided. The method comprises: determining whether a host device is requesting a sequential read access to the flash memory; prior to receiving a first host read command issued by the host device, performing a read-ahead operation to read data from the flash memory according to a read-ahead start logical block address (LBA) if the host device is requesting the sequential read access to the flash memory; and storing the data that is read through the read-ahead operation in a read-ahead buffer; and in response to receiving a first host read command issued by the host device, sending a portion or all of data that is read through the read-ahead operation to the host device if a start LBA of the first host read command corresponds to one of start LBAs of data that is stored in the read-ahead buffer.

Abstract: An input/output (I/O) interface circuit, disposed within a flash memory controller and to be coupled to a flash memory externally coupled to the flash memory controller through an I/O signal port of the flash memory controller, includes a transmission and on-die termination circuit operating as either an output driving stage circuit or an input on-die termination stage circuit. The transmission and on-die termination circuit operates as the output driving stage circuit to transfer and drive a transmission signal, sent from the processor circuit of the flash memory controller, to the flash memory through the I/O signal port. The transmission and on-die termination circuit operates as the input on-die termination stage circuit for generating and providing a matching termination resistance for the I/O signal port.

Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: An interface circuit includes a signal processing circuit including multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, a processor and a calibration circuit. The monitor circuits monitor at least one of an amplitude, a frequency and a jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The processor collects the monitored results and determines a calibration operation based on the monitored results. The calibration circuit is coupled to the processor and at least one signal processing device and performs the calibration operation on the signal processing device to adjust a characteristic value of the signal processing device.

Abstract: Disclosed is a memory device with dual interface, test method and test system thereof. An initialization procedure is executed by the memory device with dual interface in a PCIe mode. A voltage level of a pin of the memory device with dual interface is altered according to the initialization procedure, wherein the pin of the memory device with dual interface operates in a SD mode but not in PCIe mode. The voltage level of the pin of the memory device with dual interface is switched between a high voltage level and a low voltage level at a first frequency during a test stage of the initialization procedure. The voltage level of the pin of the memory device with dual interface is kept at the high voltage level or the low voltage level during a result display stage of the initialization procedure.

Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.

Abstract: A method for performing mapping table management of a memory device in a predetermined communications architecture with aid of table analysis and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; and in response to the first command, loading a local logical-to-physical (L2P) address mapping table from a non-volatile (NV) memory into a volatile memory within the memory controller to be a temporary L2P address mapping table, changing multiple L2P table entries in the temporary L2P address mapping table to be multiple updated L2P table entries in a group-by-group manner, rather than an entry-by-entry manner, and updating the local L2P address mapping table in the NV memory according to the multiple updated L2P table entries of the temporary L2P address mapping table.

Abstract: A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.

Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

Abstract: A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.