Abstract: The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer.

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract: Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods.

Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.

Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semi-conductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.

Abstract: Methods and apparatus are described for a two-axis tracking mechanism for a concentrated photovoltaic system. Two or more components forming the support structure of the two-axis tracker mechanism, which are assembled in the field and manufactured to allow one or more lasers to align the support structure of the two-axis tracker mechanism in three dimensions, vertical (X) dimension, horizontal (Y) dimension, and diagonal (Z) dimension, at a site where the concentrated photovoltaic system is to be installed. Adjustable leveling mechanisms are built into the two or more components forming the support structure.

Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localized positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.

Abstract: Embodiments of the invention relate to methods and structures for fabricating semiconductor structures that include at least one bonding layer for attaching two or more elements to one another. The at least one bonding layer may be at least substantially comprised of zinc, silicon and oxygen.

Abstract: A chromium-free etching composition suitable for treating various silicon-containing surfaces, including strained silicon on insulator surfaces as well as stressed silicon surfaces. The etching composition invention includes hydrofluoric acid, nitric acid, acetic acid and an alkali iodide, preferably potassium iodide, present in an amount of 1 mmol/100 ml or more.

Abstract: The disclosure relates to a semiconductor structure comprising: a first semiconductor layer, a first program transistor, and a first select transistor implementing a first antifuse cell, wherein the first semiconductor layer acts as the body of the first program transistor and as the body of the first select transistor, wherein a gate of the first program transistor and a gate of the first select transistor are on different sides of the first semiconductor layer.

Abstract: The invention relates to a method for testing a semiconductor substrate (1) for radiofrequency applications, characterized in that the electrical resistivity profile of the substrate as a function of depth, is measured and, using the profile, a criterion is calculated, defined by the formula (I): where D is the integration depth, ?(x) is the electrical conductivity measured at a depth x in the substrate, and L is a characteristic attenuation length of the electric field in the substrate. The invention also relates to a method for selecting a semiconductor substrate (1) for radiofrequency applications and to a device for implementing these methods.

Abstract: A gas injector includes a base plate, a middle plate, and a top plate. The base plate, middle plate, and top plate are configured to flow a purge gas between the base plate and the middle plate and to flow a precursor gas between the middle plate and the top plate. Another gas injector includes a precursor gas inlet, a lateral precursor gas flow channel, and a plurality of precursor gas flow channels. The plurality of precursor gas flow channels extend from the at least one lateral precursor gas flow channel to an outlet of the gas injector. Methods of forming a material on a substrate include flowing a precursor between a middle plate and a top plate of a gas injector and flowing a purge gas between a base plate and the middle plate of the gas injector.

Abstract: The present disclosure provides methods for treating a part made from a decomposable semiconductor material, and particularly, methods for detaching a surface film from the rest of such part. According to the provided methods, a burst or pulse of light particles of short duration and very high intensity is applied to the part in order to selectively heat, under substantially adiabatic conditions, an area of the part located at a predefined depth from the surface to a temperature higher than the decomposition temperature of the material, and subsequently a surface film is detached from the rest of the part at the heated area. In preferred embodiments, the decomposable semiconductor material comprises Ga, or comprises AlxGayIn1-x-yN, where 0?x?1, 0?y?1 and x+y?1.

Abstract: A method of fabricating a device layer structure includes providing a III-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the III-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the III-nitride semiconductor layer.

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.

Abstract: Systems for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment is optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.

Abstract: The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure.

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.

Abstract: Deposition chambers (102) for use with deposition systems (100) include a chamber wall (112) comprising a transparent material. The chamber wall may include an outer metrology window (122) surface extending from and at least partially circumscribed by an outer major surface of the wall, and an inner metrology window surface extending from and at least partially circumscribed by an inner major surface of the wall. The window surfaces may be oriented at angles to the major surfaces. Deposition systems include such chambers. Methods include the formation of such deposition chambers. The depositions systems and chambers may be used to perform in-situ metrology.