Patents Assigned to Soitec
  • Methods and structures for forming integrated semiconductor structures
    Patent number: 9034727
    Abstract: The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: May 19, 2015
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Radu Ionut
  • Method for manufacturing a semiconductor substrate
    Patent number: 9035474
    Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 19, 2015
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant, Konstantin Bourdelle, Bich-Yen Nguyen
  • DEPOSITION SYSTEMS HAVING DEPOSITION CHAMBERS CONFIGURED FOR IN-SITU METROLOGY WITH RADIATION DEFLECTION AND RELATED METHODS
    Publication number: 20150128860
    Abstract: Deposition chambers (102) for use with deposition systems (100) include a chamber wall (112) comprising a transparent material. The chamber wall may include an outer metrology window (122) surface extending from and at least partially circumscribed by an outer major surface of the wall, and an inner metrology window surface extending from and at least partially circumscribed by an inner major surface of the wall. The window surfaces may be oriented at angles to the major surfaces. Deposition systems include such chambers. Methods include the formation of such deposition chambers. The depositions systems and chambers may be used to perform in-situ metrology.
    Type: Application
    Filed: May 24, 2013
    Publication date: May 14, 2015
    Applicant: Soitec
    Inventors: Claudio Canizares, Ding Ding
  • MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES
    Publication number: 20150122313
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate with a lower surface and an upper surface; providing a second substrate with a lower surface and an upper surface; bonding the first substrate to the second substrate at the upper surface of the first substrate and the lower surface of the second substrate; and subsequently forming at least one first solar cell layer on the lower surface of the first substrate and at least one second solar cell layer at the upper surface of the second substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 7, 2015
    Applicant: SOITEC
    Inventors: Bruno Ghyselen, Chantal Arena, Matteo Piccin, Frank Dimroth, Matthias Grave
  • Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods
    Patent number: 9023721
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Method for forming a Ge on III/V-on-insulator structure
    Patent number: 9018678
    Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Soitec
    Inventors: Nicolas Daval, Bich-Yen Nguyen, Cecile Aulnette, Konstantin Bourdelle
  • Method for making a composite substrate and composite substrate according to the method
    Patent number: 9011598
    Abstract: The present invention provides methods for fabricating a composite substrate including a supporting substrate and a layer of a binary or ternary material having a crystal form that is non-cubic and semi-polar or non-polar. The methods comprise transferring the layer of a binary or ternary material from a donor substrate to a receiving substrate.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 21, 2015
    Assignee: Soitec
    Inventors: Alice Boussagol, Frédéric Dupont, Bruce Faure
  • III-V semiconductor structures and methods for forming the same
    Patent number: 9012919
    Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: April 21, 2015
    Assignee: Soitec
    Inventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
  • Method and apparatus for bonding together two wafers by molecular adhesion
    Patent number: 9004135
    Abstract: The invention provides a method of bonding a first wafer onto a second wafer by molecular adhesion, the method comprising applying a point of initiation of a bonding wave between the first and second wafers, the method further comprising projecting a gas stream between the first wafer and the second wafer generally toward the point of initiation of the bonding wave while the bonding wave is propagating between the wafers. The invention also provides a bonding apparatus for carrying out the bonding method.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: April 14, 2015
    Assignee: Soitec
    Inventors: Arnaud Castex, Marcel Broekaart
  • Process for bonding two substrates
    Patent number: 8999090
    Abstract: The invention relates to a method for bonding two substrates, in particular, two semiconductor substrates that, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: April 7, 2015
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Fabrice Lallement, Cyrille Colnat, Pascale Giard
  • Method for curing defects in a semiconductor layer
    Patent number: 8993461
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Substrate cutting device and method
    Patent number: 8991673
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Bonded semiconductor structures and method of forming same
    Patent number: 8987114
    Abstract: Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: March 24, 2015
    Assignee: SOITEC
    Inventors: Carlos Mazure, Bich-Yen Nguyen, Mariam Sadaka
  • Semiconductor structures including fluidic microchannels for cooling and related methods
    Patent number: 8980688
    Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • III-V semiconductor structures with diminished pit defects and methods for forming the same
    Patent number: 8975165
    Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 10, 2015
    Assignee: Soitec
    Inventors: Christophe Figuet, Ed Lindow, Pierre Tomasini
  • MANUFACTURE OF MULTIJUNCTION SOLAR CELL DEVICES
    Publication number: 20150059832
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a final base substrate; providing a first engineered substrate comprising a first zipper layer and a first seed layer; providing a second substrate; transferring the first seed layer to the final base substrate; forming at least one first solar cell layer on the first seed layer after transferring the first seed layer to the final base substrate, thereby obtaining a first wafer structure; forming at least one second solar cell layer on the second substrate, thereby obtaining a second wafer structure; and bonding the first and the second wafer structure to each other.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 5, 2015
    Applicant: SOITEC
    Inventors: Bruno Ghyselen, Chantal Arena, Frank Dimroth, Matthias Grave
  • Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
    Patent number: 8970045
    Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 3, 2015
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Method to thin a silicon-on-insulator substrate
    Patent number: 8962492
    Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 24, 2015
    Assignee: Soitec
    Inventors: Patrick Reynaud, Ludovic Ecarnot, Khalid Radouane
  • Method for manufacturing a semiconductor-on-insulator structure having low electrical losses
    Patent number: 8962450
    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 24, 2015
    Assignee: Soitec
    Inventors: Patrick Reynaud, Sébastien Kerdiles, Daniel Delprat
  • Moveable carrier for photovoltaic modules
    Patent number: D727842
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 28, 2015
    Assignee: Soitec Solar GmbH
    Inventors: Antoine Auberton-Herve, Jean-Luc Delcari, Gilles Du Sordet