Patents Assigned to Soitec
  • Patent number: 9835377
    Abstract: A support device that has a central axis and includes three uprights extending substantially parallel to the central axis, a plurality of series of support members spaced along the central axis, each series of support members comprising three support members adapted to support one wafer of the plurality of wafers and extending in different essentially longitudinal directions transverse to the central axis, each support member being mounted directly on a separate upright, this support device being remarkable in that the directions of the three support members of each series of support members are concurrent at a point on the central axis.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: December 5, 2017
    Assignee: Soitec
    Inventors: Christophe Gourdel, Alexandre Barthelemy
  • Patent number: 9824915
    Abstract: The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 21, 2017
    Assignees: Soitec, Peregrine Semiconductor Corporation
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Sinan Goktepeli, Anthony Mark Miscione, Alain Duvallet
  • Patent number: 9818874
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 14, 2017
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Patent number: 9812371
    Abstract: The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 7, 2017
    Assignee: Soitec
    Inventor: Thierry Barge
  • Patent number: 9805969
    Abstract: A calibration method for determining temperature set point corrections to be applied to the nominal temperature set points of each of the N heating zones of a heat treatment unit having L substrate locations, includes the following steps: establishing a sensitivity model linking variations of a substrate characteristic at each of M representative locations of the L locations to temperature set point variations applied in each of the N heating zones, the variations respectively reflecting differences with respect to a target characteristic and with respect to the nominal set points; executing the process in the heat treatment unit and on the basis of nominal set points; measuring the substrate characteristic at least at a representative measurement location of each heating zone of the unit to supply M measurements; and determining temperature set point corrections from the sensitivity model, the measurements and the target substrate characteristic.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: October 31, 2017
    Assignee: Soitec
    Inventors: Sebastien Mougel, Didier Masselin
  • Patent number: 9799549
    Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 24, 2017
    Assignee: Soitec
    Inventors: Sebastien Kerdiles, Guillaume Chabanne, Francois Boedt, Aurelia Pierret, Xavier Schneider, Didier Landru
  • Patent number: 9793360
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: October 17, 2017
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 9768057
    Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 19, 2017
    Assignee: Soitec
    Inventors: Ludovic Ecarnot, Nicolas Daval, Nadia Ben Mohamed, Francois Boedt, Carole David, Isabelle Guerin
  • Patent number: 9759546
    Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to th
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 12, 2017
    Assignees: Soitec, STMICROELECTRONICS (Crolles 2) SAS
    Inventors: Oleg Kononchuk, Didier Dutartre
  • Patent number: 9728458
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 8, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9718261
    Abstract: A method for assembling two substrates by molecular adhesion comprises: a first step (a) of putting first and second substrates in close contact in order to form an assembly having an assembly interface; a second step (b) of reinforcing the degree of adhesion of the assembly beyond a threshold adhesion value at which water is no longer able to diffuse along the assembly interface. The method also comprises a step (c) of anhydrous treatment of the first and second substrates in a treatment atmosphere having a dew point below ?10° C., and control of the dew point of a working atmosphere to which the first and second substrates are exposed from the anhydrous treatment step (c) until the end of the second step (b) so as to limit or prevent the appearance of bonding defects at the assembly interface.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 1, 2017
    Assignees: SOITEC, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Landru, Capucine Delage, Franck Fournel, Elodie Beche
  • Patent number: 9716164
    Abstract: Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventor: Mariam Sadaka
  • Patent number: 9716148
    Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 25, 2017
    Assignee: Soitec
    Inventor: Christiaan J. Werkhoven
  • Patent number: 9716029
    Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that are distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into a donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
  • Patent number: 9698063
    Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: July 4, 2017
    Assignee: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
  • Patent number: 9679799
    Abstract: The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment step is designed to partially dissolve the silicon dioxide layer, the heat treatment step being carried out in a non-oxidizing atmosphere and the pressure of the non-oxidizing atmosphere being lower than 0.1 bar.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 13, 2017
    Assignee: SOITEC
    Inventors: Christophe Gourdel, Oleg Kononchuk
  • Patent number: 9679777
    Abstract: A method for separating a structure from a substrate through electromagnetic irradiations (EI) belonging to a spectral range comprises the steps of a) providing the substrate, b) forming an absorbent separation layer on the substrate, c) forming the structure to be separated on the separation layer, d) exposing the separation layer to the electromagnetic irradiations (EI) via the substrate such that the separation layer breaks down under the effect of the heat stemming from the absorption, the method being notable in that it comprises a step b1) of forming a transparent thermal barrier layer on the separation layer, the exposure period and the thickness of the thermal barrier layer being adapted such that the temperature of the structure to be separated remains below a threshold during the exposure period, beyond which threshold, faults are likely to appear in the structure.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 13, 2017
    Assignee: Soitec
    Inventors: Yann Sinquin, Jean-Marc Bethoux, Oleg Kononchuk
  • Patent number: 9659777
    Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 23, 2017
    Assignee: Soitec
    Inventors: Didier Landru, Carole David, Ionut Radu, Lucianna Capello, Yann Sinquin
  • Patent number: 9653536
    Abstract: A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: May 16, 2017
    Assignee: Soitec
    Inventors: Alexandre Chibko, Isabelle Bertrand, Sylvain Peru, Sothachett Van, Patrick Reynaud
  • Publication number: 20170133347
    Abstract: A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 11, 2017
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, SOITEC
    Inventors: Hubert MORICEAU, Bruno IMBERT, Xavier BLOT