Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters comprises providing a substrate including a medium, a flow layer disposed on the medium, and a plurality of strained crystalline semiconductor islands having an initial lattice parameter arranged on the flow layer. The strained semiconductor islands are selectively treated so as to form a first group of strained islands having a first lateral expansion potential, and a second group of strained islands having a second lateral expansion potential that is different from the first lateral expansion potential. The substrate is heat treated at a temperature at or above a glass transition temperature of the flow layer to cause differentiated relaxation of the islands of the first and second groups, such that a lattice parameter of the first group of relaxed islands differs from a lattice parameter of the second group of relaxed islands.

Abstract: A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on a major surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.

Abstract: A method of transferring blocks of semiconductor material to a substrate comprises the following steps: a. providing an intermediate substrate, the intermediate substrate comprising, on one of its faces, blocks, the blocks comprise a monocrystalline material, the blocks comprising an embrittlement area delimiting a block portion intended to be transferred onto a final substrate; b. executing an assembling step by putting the free surface of each of the blocks in contact with the final substrate; c. executing, after the assembling step, detachment at the embrittlement area of each of the blocks. During the assembling step, the intermediate substrate deforms so that the free surfaces of the blocks become coplanar.

Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the semiconductor substrate.

Abstract: A method of producing a structure made of a piezoelectric material, including: a) production of a stack including at least one metal layer and at least one conductive layer on a substrate made of piezoelectric material, wherein at least one electrical contact is established between the conductive layer and a metal element outside the stack; b) an ionic and/or atomic implantation, through the conductive layer and the metal layer; c) transfer of the substrate onto a transfer substrate, followed by fracturing of the transferred piezoelectric substrate, in an embrittlement area.

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1?wN, and at least one barrier layer comprising InbGa1?bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1?wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1?bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.

Abstract: The invention relates to a process for transferring an active layer to a final substrate using a temporary substrate, the active layer comprises a first side having a three-dimensional surface topology, the process comprising: a first step of bonding the first side of the active layer to one side of the temporary substrate; a second step of bonding a second side of the active layer to the final substrate; and a third step of separating the active layer and the temporary substrate; the process being characterized in that the side of the temporary substrate possesses a surface topology complementary to the surface topology of the first side of the active layer, so that the surface topology of the temporary substrate encapsulates the surface topology of the first side of the active layer in the bonding first step.

Abstract: This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.

Abstract: A process is used for fabricating a final structure comprising in succession a useful semiconductor layer, a dielectric layer and a carrier substrate. The process comprises providing an intermediate structure including an upper layer, the dielectric layer and the carrier substrate, and finishing the intermediate structure to form the final structure by performing a treatment nonuniformly modifying the thickness of the dielectric layer following a predetermined dissolution profile. The dielectric layer of the intermediate structure has a thickness profile complementary to the predetermined dissolution profile.

Abstract: A method for transferring a useful layer onto a carrier substrate comprises formation of an embrittlement plane by implantation of light species into a first substrate in such a manner as to define the bounds of a useful layer between the plane and a surface of the first substrate, mounting of the carrier substrate onto a surface of the first substrate so as to form an assembly to be fractured, and thermal fracture treatment of the first substrate along the embrittlement plane in such a manner as to transfer the useful layer onto a support. During the thermal fracture treatment, the degree of peripheral adhesion is reduced at an interface between the carrier substrate and the first substrate.

Abstract: This disclosure relates to a device for separating two substrates to be utilized in electronics, optics, optoelectronics and/or photovoltaics. The device separates the substrates at an interface, the device comprising a holder; a member for retaining the structure, the member being mounted on the holder; a tool for separating the two substrates, also mounted on the holder; and means for moving the separating tool and/or means for moving the retaining member relative to the holder so as to bring them closer together or move them farther apart from each other, preferably over a limited range of travel. This device is noteworthy in that the separating tool comprises a leading edge that has, in cross-section, in succession from its tip or its front edge to its back, a tapered portion that is extended by a flared portion.

Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.

Abstract: The disclosure relates to a process for treating a structure, the structure comprising, from its back side to its front side, a carrier substrate, an insulating layer and a useful layer, the useful layer having a free surface, the structure being placed in an atmosphere containing chemical species, the chemical species being capable of reacting chemically with the useful layer. This treatment process is noteworthy in that the useful layer is heated by a pulsed laser beam, the beam sweeping the free surface, the wavelength of the beam differing by, at most, plus or minus 15 nm from a central wavelength, the central wavelength being chosen so that the sensitivity of the reflectivity of the structure relative to the insulating layer is zero.

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.

Abstract: A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support substrate; b) forming a zone of weakening in the donor substrate, the zone of weakening delimiting, with the first surface of the donor substrate, a working layer; c) assembling the support substrate and the donor substrate; d) fracturing the donor substrate along the zone of weakening; and e) thinning the working layer so as to form a thinned working layer. Stage b) is carried out so that the working layer exhibits a thickness profile appropriate for compensating for the nonuniformity in consumption of the working layer during stage e).

Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.

Abstract: A process comprises the following steps: a) provision of a chamber suitable for receiving a plurality of structures, b) circulation of a gas stream in the chamber so that the chamber has a non-oxidizing atmosphere, c) heat treatment of the plurality of structures at a temperature above a threshold value above which the oxygen present in an oxide of a dielectric diffuses through an active layer reacts with semiconductor material of the active layer and produces a volatile material, the process being noteworthy in that the step b) is carried out so that the gas stream has a rate of circulation between the plurality of structures greater than the rate of diffusion of the volatile material into the gas stream.

Abstract: The disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate.