Abstract: A method for separating a structure from a substrate through electromagnetic irradiations (EI) belonging to a spectral range comprises the steps of a) providing the substrate, b) forming an absorbent separation layer on the substrate, c) forming the structure to be separated on the separation layer, d) exposing the separation layer to the electromagnetic irradiations (EI) via the substrate such that the separation layer breaks down under the effect of the heat stemming from the absorption, the method being notable in that it comprises a step b1) of forming a transparent thermal barrier layer on the separation layer, the exposure period and the thickness of the thermal barrier layer being adapted such that the temperature of the structure to be separated remains below a threshold during the exposure period, beyond which threshold, faults are likely to appear in the structure.

Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.

Abstract: A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.

Abstract: A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.

Abstract: The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite structure, a treatment step modifying the optical properties in reflection at an interface between the support substrate and the separation layer or on an upper face of the support substrate.

Abstract: Methods of depositing compound semiconductor materials on one or more substrates include metering and controlling a flow rate of a precursor liquid from a precursor liquid source into a vaporizer. The precursor liquid may comprise at least one of GaCl3, InCl3, and AlCl3 in a liquid state. The precursor liquid may be vaporized within the vaporizer to form a first precursor vapor. The first precursor vapor and a second precursor vapor may be caused to flow into a reaction chamber, and a compound semiconductor material may be deposited on a surface of a substrate within the reaction chamber from the precursor vapors. Deposition systems for performing such methods include devices for metering and/or controlling a flow of a precursor liquid from a liquid source to a vaporizer, while the precursor liquid remains in the liquid state.

Abstract: Apparatus for the industrial wiring and final testing of photovoltaic concentrator modules, consisting of a module frame, a lens disc, a sensor carrier disc and an electrical line routing arrangement, comprising the following features: a) a laser contact-making device for the contactless connection of connecting lines between the individual sensors and of connecting elements and of collective contact plates, wherein the line routing arrangement on the sensor carrier disc as basic structure has, in each case, five CPV sensors connected in parallel, and these parallel circuits are connected in series, b) a device for testing electrical properties, wherein a specific voltage is applied to CPV sensors themselves, and the light emitted by them via the lenses is detected and assessed, c) a device for testing tightness of finished concentrator modules, wherein compressed air is applied to the modules in the interior and the emission of compressed air is checked.

Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A?, B, B?); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract: A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of the parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface.

Abstract: The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is attached to a surface of the cooling substrate by a thermally conductive adhesive and electrically contacted to the bonding pad and cooling substrate by a bonding wire. Alternatively, the bonding pad is attached to a surface of the cooling substrate by a thermally and electrically conductive adhesive.

Abstract: A method for transferring a useful layer onto a support includes the following processes: formation of a fragilization plane through the implantation of light species into a first substrate in such a way as to form a useful layer between this plane and a surface of the first substrate; application of the support onto the surface of the first substrate to form an assembly to be fractured having two exposed sides; thermal fragilization treatment of the assembly to be fractured; and initiation and self-sustained propagation of a fracture wave in the first substrate along the fragilization plane. At least one of the sides of the assembly to be fractured is in close contact, over a contact zone, with an absorbent element suitable for capturing and dissipating acoustic vibrations emitted during the initiation and/or propagation of the fracture wave.

Abstract: A process for transferring a useful layer to a receiver substrate includes providing a donor substrate comprising an intermediate layer, a carrier substrate, and a useful layer. The intermediate layer is free of species liable to degas during a subsequent heat treatment, and is configured to become soft at a temperature. The receiver substrate and the donor substrate are assembled. An additional layer is provided between the receiver substrate and the carrier substrate that comprises chemical species that are susceptible to diffuse into the intermediate layer during the subsequent heat treatment so as to form a weak zone. The heat treatment is carried out on the receiver substrate and the donor substrate at a second temperature higher than the first temperature.

Abstract: A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, the routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate.

Abstract: The invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. The invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.

Abstract: This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array,—at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.