Abstract: A photonic interconnection elementary switch is integrated in an optoelectronic chip/The switch includes first and second linear optical waveguides which intersect to form a first intersection. Two first photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. Two second photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. A third linear optical waveguide is coupled to one of the first ring resonators and one of the second ring resonators. A fourth linear optical waveguide is coupled to another of the first resonators and to another of the second ring resonators. A base switch, complex switch, and photonic interconnection network integrated in an optoelectronic chip, include at least two of the photonic interconnection elementary switches.

Abstract: A power transistor generates an output current and a sense transistor generates a proportional sense current. A differential amplifier generates a gate voltage applied to the power and sense transistors in response to first and second input signals. A comparator circuit compares the gate voltage to a switching reference to detect whether the power and sense transistors are operating in a triode mode of operation or in a saturation mode of operation. At least one of the first and second input signals is modified in response to the detection made by the comparator circuit. In one instance, different reference voltages are applied to an input of the amplifier depending on the detected mode of operation. In another instance, different resistances are used to convert the sense current to a voltage for application to an input of the amplifier in response to the detected mode of operation.

Abstract: A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Abstract: The transmission device comprising a transmit stage configured to deliver a transmission signal on an input-output node of an antenna and comprising a power transistor coupled to the input-output node and configured to amplify a signal to be transmitted. The device comprises a receive stage configured to receive a reception signal on the input-output node and comprising an attenuator circuit configured to attenuate the reception signal. The attenuator circuit comprising the power transistor and a control circuit able to place the power transistor in a triode mode.

Abstract: A system and method for synchronizing two devices in communication with each other. When communication between the two devices is to be established, a synchronization process may be invoked. In an embodiment, a first device may initiate sending synchronization signals having rising edge and falling edge pairs. The second device may include a controller configured to receive the synchronization signals. However, noise may inhibit the ability of the controller to correctly receive and/or interpret the synchronization signals. Noise may cause detection components to falsely detect noise as a synchronization signal or may cause detection components to miss detection of an actual synchronization signal. A window generator may be used to generate comparison windows for the controller to detect synchronization signals.

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

Abstract: An analog multiplexer includes inputs and one output. A switching circuit is coupled between each input and the output. Each switching circuit includes an NMOS switching module, having an on state and an off state, and a control module supplied by a first supply voltage and operating to reduce leakage currents of the NMOS switching module when in the off state. The control module further operates to make the first NMOS switching module bidirectional irrespective of voltages present at the input and at the output.

Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.

Abstract: A photodiode produces photogenerated charges in response to exposure to light. An integration period collects the photogenerated charges. Collected photogenerated charges in excess of an overflow threshold are passed to an overflow sense node. Remaining collected photogenerated charges are passed to a sense node. A first signal representing the overflow photogenerated charges is read from the overflow sense node. A second signal representing the remaining photogenerated charges is read from the sense node.

Abstract: An optical waveguide includes opposed end sections for optical radiation to propagate in a longitudinal direction therebetween and an intermediate section extending between the end sections. The intermediate section includes first and second portions superposed in a superposition direction. One of the opposite end sections has a first height in the superposition direction corresponding to the sum of the heights of the superposed portions of the intermediate section. The other of the opposite end sections has a second height in the superposition direction corresponding to the height of the first of the superposed portions of the intermediate section.

Abstract: A method for making an electro-optic device includes forming a first photonic device having a first material in a first photonic layer over a substrate layer. A second photonic layer with a second photonic device is formed over the first photonic layer and includes a second material different than the first material. A dielectric layer is formed over the second photonic layer. A first electrically conductive via extending through the dielectric layer and the second photonic layer is formed so as to couple to the first photonic device. A second electrically conductive via extending through the dielectric layer and coupling to the second photonic device is formed. A third electrically conductive via extending through the dielectric layer, the second photonic layer, and the first photonic layer is formed so as to couple to the substrate layer.

Abstract: An integrated electronic device, for detecting for detecting changes in an environmental parameter indicative of an environment surrounding the device, includes: a first conductive element and a second conductive element; a measurement circuit including a first measurement terminal and a second measurement terminal respectively coupled to the first conductive element and the second conductive element. The measurement circuit is configured to provide an electrical potential difference between the first conductive element and the second conductive element is configured to determine a change in an impedance of an electromagnetic circuit including the first conductive element and the second conductive element and formed between the first measurement terminal and the second measurement terminal. The device determines that an increase in a presence of water within the environment has occurred in response to a decrease in a real part of the impedance of the electromagnetic circuit.

Abstract: A signal is protected against an attack by an enhancement process that checks the conformity of an actual state of the signal with respect to an expected state. A protective action is exercised on the signal if the actual state of the signal is not in conformity with the expected state, so as to neutralize or nullify said attack.

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. The metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition with process parameters selected so as to produce grains of material exhibiting a uniaxial grain orientation. The uniaxial grain structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

Abstract: A method of encoding an initial digital signal in an encoded signal, where the initial digital signal includes a sequence of samples representing a multidimensional space, and each sample may be assigned at least one physical magnitude. The method may include, for at least some of the current samples, locally encoding the signal in encoded local digital signals, with the encodings being performed in local reference frames each including the current sample considered and two reference samples. The reference samples may be chosen based upon a minimum gradient of the at least one physical magnitude, from among the available samples of the sequence, and the encoded signal may include the encoded local digital signals.