Abstract: A compensation circuit receives a sensing signal from a Hall sensor and outputs a compensated Hall sensing signal. The compensation circuit has a gain that is inversely proportional to Hall sensor drift mobility. The compensated Hall sensing signal is temperature-compensated.

Abstract: A circuit module of an integrated circuit is located in a first zone of a semiconductor substrate. A decoy cell includes an antenna above a second zone of the semiconductor substrate. The second zone is different from the first zone. A generation circuit operates to generate a decoy electrical signal on the basis of a first electrical signal that is characteristic of an operation of the circuit module and of at least one pseudo-random parameter. The decoy electrical signal is circulated through the antenna so as to generate a decoy electromagnetic radiation.

Abstract: Hall sensing signals are received in a spinning readout pattern of subsequent readout phases, wherein the pattern is cyclically repeated at a spinning frequency and a polarity of the Hall sensor signals is reversed in two non-adjacent readout phases of the readout pattern. A signal storage circuit includes signal storage capacitors. An accumulation circuit includes accumulation capacitors. A switch network is selectively actuated to couple the signal storage capacitors with the accumulation capacitors synchronously with phases in the spinning readout pattern in subsequent alternating first and second periods. The spinning output is stored with alternating opposite signs on the signal storage capacitors and the Hall sensing signals are stored in the signal storage capacitors and then accumulated on the accumulation capacitors with alternate signs in subsequent periods. The accumulated output signal is then demodulated with a demodulation frequency half the spinning frequency.

Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.

Abstract: A touch screen controller includes input circuitry receiving touch data from the touch screen. Processing circuitry acquires touch data from the input circuitry in a self-capacitance sensing mode, locates a force island and locates a sense island. A length of the force island and a length of the sense island is calculated. If the length of the force island is greater than a threshold force length and if the length of the sense island is greater than a threshold sense length, then the product of the lengths is calculated, and if greater than a threshold size, designated a valid area. Touch data in the valid area is then acquired in mutual-capacitance sensing mode, and represents palm touch if a maximum strength value in the valid area is less than a maximum area threshold and if a minimum strength value in the valid area is greater than a minimum area threshold.

Abstract: A converter includes first and second input terminals and first and second output terminals. The converter also includes an output capacitor coupled between the first output terminal and the second output terminal, and a magnetic component having two input terminals and three output terminals. A first output terminal of the magnetic component is coupled through a first electronic switch to the second output terminal of the converter, a second output terminal of the magnetic component is coupled to the first output terminal of the converter, and a third output terminal of the magnetic component is coupled through a second electronic switch to the second output terminal of the electronic converter. In addition, the converter includes a switching stage configured to transfer current pulses from the first input terminal and the second input terminal of the converter to the two input terminals of the magnetic component.

Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.

Abstract: A control device for a switching regulator having two or more converter stages operating with interleaved operation, each converter stage including an inductive element and a switch element, generates command signals having a switching period for controlling switching of the switch elements, and determining alternation of a storage phase of energy in the respective inductive element and a transfer phase of the stored energy onto an output element. The control device generates the command signals phase-offset by an appropriate fraction of the switching period to obtain interleaved operation. In particular, a synchronism stage generates a synchronism signal and a control stage generates the command signals for the converter stages timed by the same synchronism signal.

Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.

Abstract: A security module has an assigned unique electronic identifier. The security module has a communication interface, a non-volatile memory, and a processing unit coupled to the communication interface and the non-volatile memory. One or more unassigned secure domains are formed in the non-volatile memory, and each of the unassigned secure domains has an assigned unique application identifier (AID). Each of the unassigned secure domains is accessible via a respective first security value, and using the respective first security value, each of the unassigned secure domains can be assigned to a service provider before or after the security module is deployed.

Abstract: A signal interface has a compression unit and a data memory. The compression unit is configured to input an input datum from signal data generated by at least one sensor and further configured to identify the presence or absence of at least one repetition condition in the input datum. If the presence of the at least one repetition condition of the input datum is identified, the compression unit encodes the input datum in a compressed way to generate a compressed datum and saves the compressed datum in the data memory. If the presence of the at least one repetition condition of the input datum is not identified, the compression unit saves the uncompressed input datum in the data memory.

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.

Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.

Abstract: A transmission chain receives an incident signal to be transmitted having a first power and a first bandwidth. A first modulator frequency shifts a first signal derived from the incident signal to generate a first shifted signal at a modulation output. A power amplifier coupled to the modulation output amplifies an intermediate signal to generate an amplified output signal. A predistortion-signal-generating circuit generates, from the incident signal and from the amplified output signal in a second bandwidth that is larger than the first bandwidth, a predistortion signal having a second power lower than the first power. A second modulator frequency shifts a second signal derived from the predistortion signal to generate a second shifted signal for combination with the first shifted signal at said modulation output to produce the intermediate signal.

Abstract: An electronic device includes a power switch having a control terminal coupled to a first node, a first conduction terminal coupled to a second node, and a second conduction terminal coupled to a third node. A monitoring circuit has a first input coupled to the first node and a second input coupled to the second node, the monitoring circuit to generate a monitor signal indicating gate oxide stress on the power switch as a function of first and second voltages received at the first and second inputs thereof. A protection circuit actuates to protect the power switch from the gate oxide stress when the monitor signal indicates the gate oxide stress on the power switch. The monitoring signal is generated based upon a comparison of currents generated based upon the voltages at the first and second node, as well as a current generated based upon a programmable reference voltage.

Abstract: A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.