Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

Abstract: A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

Abstract: A support plate has a front face with an electronic chip mounted on the front face. A cover for encapsulating the electronic chip includes a front wall extending in front of the electronic chip and a peripheral wall having an end edge fixed on a peripheral area of the support plate. The support plate and the encapsulating cover define a chamber in which the electronic chip is located. A local slot is arranged to extend between the peripheral wall of the encapsulating cover and the support plate. The local slot has an exterior opening and an interior opening leading into said chamber.

Abstract: A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.

Abstract: Described herein is a method of operating an electronic device that includes collecting initial motion activity data from at least one sensor of the electronic device, and generating a initial probabilistic context of the electronic device relative to its surroundings from the initial collected motion activity data using a motion activity classifier function. The collected motion activity data is stored in a training data set, and the motion activity classifier function is updated using the training data set. The method also includes collecting subsequent motion activity data from the at least one sensor of the electronic device, and generating a subsequent probabilistic context of the electronic device relative to its surroundings from the subsequently collected motion activity data using the updated motion activity classifier function.

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

Abstract: A control method for real-time scene detection by a wireless communication apparatus equipped with at least one environmental measurement sensor is disclosed. A temporal adjustment of the instants of activation of the detection is based on measurement values delivered by the at least one environmental measurement sensor at instants of measurement.

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Abstract: A communication method includes receiving a first message of a Short Message Service containing a first command that requests execution of a proactive command. The first message is decrypted according to protocol SCP80 to extract the first command. The execution of the proactive command is requested in order to obtain a response to the proactive command. A second message of the Short Message Service is transmitted to the remote server and indicates that the response to the proactive command has been obtained. A third message of the Short Message Service is received and contains a second command from the remote server. The third message is decrypted according to the protocol SCP80. A response message is generated as a function of the response and encrypted according to the protocol SCP80 to generate a fourth message of the Short Message Service transmitted to the remote server.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, first discontinuous slotted recesses in a first surface of a wafer. The first discontinuous slotted recesses may be arranged in parallel, spaced apart relation. The method may further include forming, by sawing with the rotary saw blade, second discontinuous slotted recesses in a second surface of the wafer aligned and coupled in communication with the first continuous slotted recesses to define through-wafer channels. In another embodiment, the first and second plurality of discontinuous recesses may be formed by respective first and second rotary saw blades.

Abstract: A method forms a vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are formed adjacent respective sidewalls of the semiconductor substrate. The method forms dielectric material separating the gate electrodes from the source and drain regions.

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

Abstract: The present disclosure includes a method that includes generating a decoded output signal that corresponds to reflected light received by a plurality of single photon avalanche diodes (SPAD) by removing ambient light from a plurality of SPAD array output signals. The removing of ambient light including synchronizing the plurality of SPAD array output signals by using a plurality of parallel time to digital converters, each time to digital converter outputting a synchronized SPAD array output signal, determining a plurality of flexible thresholds for each one of the synchronized SPAD array output signals, comparing current data on the synchronized SPAD array output signals with the respective ones of the flexible threshold in a filter, and outputting the first output signal.

Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.

Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.

Abstract: An IC card includes a first visible layer including a natural material having a unique visual pattern. A storage device is configured to store a digital reference image of the unique visual pattern to be visually compared with the unique visual pattern for authentication. An authentication method based on the IC card is also provided.