Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference comprising a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.

Abstract: An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

Abstract: A method can be used for detecting a potential presence of an object by a reader capable of mutually communicating via a contactless communications protocol. An antenna of the reader transmits a magnetic field on a carrier signal having a sub-carrier modulated by a first data sequence. The modulated sub-carrier is non-interpretable by the object. The antenna of the reader receives a signal resulting from the transmission. The reader demodulates the sub-carrier of the resulting signal so as to extract a second data sequence from the resulting signal. The first data sequence and second data sequence are correlated and the potential presence or absence of the object is determined based upon the result of the correlating.

Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.

Abstract: A capacitor having a capacitance settable by biasing, including: a series association of a plurality of first capacitive elements between two first terminals defining the capacitor electrodes; and two second terminals of application of bias voltages respectively connected, via resistive elements, to the opposite electrodes of each of the first capacitive elements.

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: Disclosed herein is a method including receiving a stream of packets into a buffer, each packet having a processed video data portion and a page count portion, the processed video data portion being a result of a modulo operation performed on a word of video data, and the page count portion being a data page number on which the word of video data is to be placed. Each packet is read from the buffer, and an output packet including the video data portion and a data tag portion is generated therefrom. The data tag portion is associated with, but does not directly represent, the data page number where the word of video data of the processed video data portion or of video data of a processed video data portion of a next packet, is to be placed. Each data tag portion contains fewer bits than each corresponding page count portion.

Abstract: A level shifter circuit includes: an input stage for receiving an input signal switchable between a first and a second input level and an output stage to produce a drive signal for the load that is switchable between a first and a second output level. A level translator translates the input signal switching between the input levels into the output stage switching between the output levels. A feedback element coupled to the output stage transfers to the input stage a feedback signal representative of the output level of the output stage. The input stage includes control circuitry sensitive to the input signal and the feedback signal for detecting undesired switching of the output stage between the first and second output levels occurring in the absence of input signal switching between the first and second input levels. The control circuitry inverts the output level of the output stage resulting from undesired switching.

Abstract: A method for manufacturing a microelectronic semiconductor device comprising the steps of: forming a trench in a body, the trench having side walls, a opening, and a bottom; forming a sacrificial layer in the trench; forming a recess in the sacrificial layer; forming a restriction structure between the sacrificial layer and the opening of the trench, defining a through hole for access to the sacrificial layer; completely removing the sacrificial layer through said through hole; and depositing a metal layer over the body, thus closing the opening of the trench and forming an electron-emission cathode tip.

Abstract: An electronic device includes a current comparator to generate an output current based upon a difference between a current flowing in an output branch and a current flowing in an input branch. A pair of transistors is coupled to an output of the current comparator. A first amplifier has inputs coupled to the pair of transistors and to a reference voltage, the first amplifier being configured to subtract the reference voltage from a voltage across the pair of transistors and output a difference voltage. A second amplifier has inputs coupled to the difference voltage and to the reference voltage, the second amplifier being configured to subtract the difference voltage from the reference voltage and output a pulse skipping mode reference signal.

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

Abstract: An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire.

Abstract: A thin film amorphous silicon solar cell may have front contact between a hydrogenated amorphous silicon layer and a transparent conductive oxide layer. The cell may include a layer of a refractory metal, chosen among the group composed of molybdenum, tungsten, tantalum and titanium, of thickness adapted to ensure a light transmittance of at least 80%, interposed therebetween, before growing by PECVD a hydrogenated amorphous silicon p-i-n light absorption layer over it. A refractory metal layer of just about 1 nm thickness may effectively shield the oxide from the reactive plasma, thereby preventing a diffused defect when forming the p.i.n. layer that would favor recombination of light-generated charge carriers.

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract: A micro-electro-mechanical device, wherein a platform is formed in a top substrate and is configured to turn through a rotation angle. The platform has a slit and faces a cavity. A plurality of integrated photodetectors is formed in a bottom substrate so as to detect the light through the slit and generate signals correlated to the light through the slit. The area of the slit varies with the rotation angle of the platform and causes diffraction, more or less marked as a function of the angle. The difference between the signals of two photodetectors arranged at different positions with respect to the slit yields the angle.

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract: A diagnostic circuit is used for detecting the load status of an audio amplifier. The audio amplifier includes two output terminals for connection to a speaker. The diagnostic circuit may include a first circuit, which configured to generate a first signal indicating whether a signal provided via the two output terminals comprises an audio signal. A second circuit can be configured to detect a first measurement signal being indicative for the output current provided via the two output terminals, and to compare the first measurement signal with at least one threshold in order to generate a second signal indicating whether the output current has a low current amplitude profile or a high current amplitude profile. A third circuit can be configured to generate a diagnostic signal as a function of the first and the second signal.

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.