Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.

Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.

Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.

Abstract: Method of manufacturing a transducer module, comprising the steps of: forming, on a substrate, a first MEMS transducer, in particular a gyroscope, and a second MEMS transducer, in particular an accelerometer, having a suspended membrane; forming, on the substrate, a conductive layer and defining the conductive layer in order to provide, simultaneously, at least one conductive strip electrically coupled to the first MEMS transducer and the membrane of the second MEMS transducer.

Abstract: The present disclosure is directed to a greenhouse or single container for plant growth coupled to the Internet of Things and including a microfluidic die for water or nutrient distribution. The microfluidic die is controllable automatically or with instructions from a remote user, based on sensors included within a growth environment.

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

Abstract: One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has recess at a perimeter of the semiconductor die. The semiconductor package includes an encapsulation layer that is located over the semiconductor die filling the recess and surrounding side surfaces of the pillars. The package may be formed on a wafer with a plurality of die and may be singulated into a plurality of packages.

Abstract: A method can be used to manufacture a charge storage cell with a first trench and a second trench in a substrate material. The first trench is filled with a doped material. The second trench is filled with a second trench material. The method includes causing the dopant to diffuse from the first trench to thereby provide a doped region adjacent to the first trench. The material from the first and second trenches is removed and at least one of the trenches is filled with a capacitive deep trench isolation material to provide capacitive deep trench isolation.

Abstract: A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.

Abstract: An integrated circuit includes an IO node, and an IO driver coupled thereto. The IO driver has a first driving circuit with a first PMOS transistor having a source coupled to a supply node and a gate coupled to receive a PMOS driving signal, and a first NMOS transistor having a source coupled to ground, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to receive a NMOS driving signal. The IO driver also has a second driving circuit with a second PMOS transistor having a source coupled to the supply node and a gate coupled to receive a first delayed version of the PMOS driving signal, and a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a source coupled to ground, and a gate coupled to receive a first delayed version of the NMOS driving signal.

Abstract: LED strings cascaded to one another are driven by an electronic circuit that includes regulation modules and a brightness-compensation module. The regulation modules carry out in sequence a current-regulation phase, in which they regulate the current that flows in the corresponding LED strings. The regulation module includes: a compensation regulator coupled to a compensation LED string and to a capacitor and a generator that generates an electrical quantity indicating the luminous flux emitted by the LED strings and by the compensation LED string. The compensation regulator regulates a current that flows in the compensation LED string as a function of the electrical quantity, discharging the capacitor through the compensation LED string.

Abstract: A method for extraction of descriptors from video content, includes the following steps: a Key Frame Extracting step, applying a local descriptors-based approach to select pictures of the incoming video as key frames that are representative of a temporal region of the video which is visually homogeneous; a Content Analysis step, analysing the content of the key frames and classifying image patches of the key frames as interesting or not for the extraction of descriptors; a Descriptors Extracting step, extracting compact descriptors from the selected key frames, and defining a set of surrounding images also on the basis of input received from the Content Analysis step; a Temporal Coding step, multiplexing information about the time points at which said key frames have been extracted in the Key Frame Extracting step with the compact descriptors extracted in the Descriptors Extracting step, obtaining the descriptors.

Abstract: A circuit of an actively transmitting tag includes an antenna, a digitizer, a voltage-controlled oscillator (VCO), an output amplifier, a phase-displacement detector, and a regulator. The input of the digitizer connects to the antenna. The outputs of the digitizer and the output amplifier are connected to the input terminals of the phase-displacement detector. The output amplifier connects the output of the VCO to the antenna and the regulator connects the output of the phase-displacement detector to the VCO.

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Abstract: The embodiments of the present disclosure provide a proximity sensor, an electronic apparatus and a method for manufacturing a proximity sensor. The proximity sensor comprises a sensor chip, a light-emitting device, a transparent molding material and a non-transparent molding material, wherein the sensor chip comprises a sensor region; the light-emitting device is located on the sensor chip and is electrically coupled to the sensor chip; the transparent molding material at least covers a light-emitting surface of the light-emitting device; and the non-transparent molding material isolates the transparent molding material from the sensor region.

Abstract: An electro-optic device may include a photonic chip having an optical grating coupler at a surface. The optical grating coupler may include a first semiconductor layer having a first base and first fingers extending outwardly from the first base. The optical grating coupler may include a second semiconductor layer having a second base and second fingers extending outwardly from the second base and being interdigitated with the first fingers to define semiconductor junction areas, with the first and second fingers having a non-uniform width. The electro-optic device may include a circuit coupled to the optical grating coupler and configured to bias the semiconductor junction areas and change one or more optical characteristics of the optical grating coupler.

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.