Patents Assigned to STMicroelectronics AS
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Patent number: 10103310Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.Type: GrantFiled: September 11, 2015Date of Patent: October 16, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: Emmanuel Dubois, Jean-Francois Robillard, Stephane Monfray, Thomas Skotnicki
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Publication number: 20180294845Abstract: A case includes a base for receiving a portable phone and a flap hinged to the base and including a housing configured to receive a microcircuit card. A first contactless communication antenna is provided in the flap for coupling to an antenna of the microcircuit card. A second contactless communication antenna is provided in the base for coupling to an antenna of the portable phone. The first and second first contactless communication antennae are electrically connected to each other.Type: ApplicationFiled: June 8, 2018Publication date: October 11, 2018Applicant: STMicroelectronics (Tours) SASInventors: Igor Bimbaud, Eric Colleoni
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Patent number: 10094876Abstract: A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.Type: GrantFiled: October 3, 2016Date of Patent: October 9, 2018Assignee: STMicroelectronics International N.V.Inventor: Danish Hasan Syed
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Patent number: 10096708Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.Type: GrantFiled: August 8, 2016Date of Patent: October 9, 2018Assignee: STMicroelectronics SAInventors: Sotirios Athanasiou, Philippe Galy
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Patent number: 10094891Abstract: An integrated AMR magnetoresistive sensor has a magnetoresistor, a set/reset coil and a shielding region arranged on top of each other. The set/reset coil is positioned between the magnetoresistor and the shielding region. The magnetoresistor is formed by a magnetoresistive strip of an elongated shape having a length in a first direction parallel to the preferential magnetization direction and a width in a second direction perpendicular to the first direction. The set/reset coil has at least one stretch extending transversely to the magnetoresistive strip. The shielding region is a ferromagnetic material and has a width in the second direction greater than the width of the magnetoresistive strip so as to attenuate the external magnetic field traversing the magnetoresistive strip and increase the sensitivity scale of the magnetoresistive sensor.Type: GrantFiled: April 22, 2016Date of Patent: October 9, 2018Assignee: STMicroelectronics S.r.l.Inventors: Dario Paci, Marco Marchesi, Marco Morelli
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Patent number: 10094797Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.Type: GrantFiled: May 25, 2017Date of Patent: October 9, 2018Assignee: STMICROELECTRONICS PTE LTD.Inventors: Olivier Le Neel, Ravi Shankar, Suman Cherian, Calvin Leung, Tien-Choy Loh, Shian-Yeu Kam
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Patent number: 10094915Abstract: A method is for estimating a distance to an object. The method may include determining, by a ranging device, a first range value based upon a time of flight of first optical pulses having a period of a first duration, and determining, by the ranging device, a second range value based upon a time of flight of second optical pulses having a period of a second duration different from the first duration. The method may include estimating the distance based upon the first and second range values.Type: GrantFiled: October 30, 2015Date of Patent: October 9, 2018Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Marc Drader, Pascal Mellot
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Patent number: 10097264Abstract: A single photon avalanche diode based apparatus comprising: at least one array of single photon avalanche diodes configured to receive light generated externally to the apparatus, wherein the at least one array is configurable to be sub-divided into a plurality of sub-arrays, each sub-array able to receive a separate free space light communication channel; and a receiver configured to receive the output from each sub-array and output data based on the received plurality of sub-array separate free space light communication channel.Type: GrantFiled: May 31, 2017Date of Patent: October 9, 2018Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventors: Aravind Venugopalan Nair Jalakumari, Neale Dutton
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Patent number: 10097182Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.Type: GrantFiled: December 31, 2015Date of Patent: October 9, 2018Assignee: STMICROELECTRONICS, INC.Inventors: Chetan Bisht, Harry Scrivener, III
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Patent number: 10096093Abstract: In one embodiment of the present invention, a method is provided for performing motion compensated interpolation using a previous frame and a current frame of a displayable output, the method comprising: detecting the speed of an object in the displayable output relative to the speed of a background in the displayable output; and blending results from a halo reducing interpolator and a median interpolator, wherein the results of each of the interpolators are weighted based on the speed of the object, to arrive at an interpolated frame using the previous frame and the current frame.Type: GrantFiled: May 11, 2017Date of Patent: October 9, 2018Assignee: STMicroelectronics, Inc.Inventor: Gordon Petrides
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Patent number: 10097799Abstract: An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.Type: GrantFiled: April 20, 2018Date of Patent: October 9, 2018Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Mahesh Chandra, Brejesh Lall
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Publication number: 20180288366Abstract: Disclosed herein is an electronic device including a first laser source configured to project a first laser beam, and a second laser source configured to project a second laser beam in alignment with the first laser beam in a first direction but at an angle with respect to the first laser beam in a second direction. A mirror apparatus is positioned so as to reflect the first and second laser beams. Control circuitry is configured to control the mirror apparatus to simultaneously reflect the first and second laser beams in a first scan pattern to form an first image, the first image formed from the first scan pattern having a number of scan lines greater than two times a horizontal resonance frequency at which the mirror apparatus oscillates divided by a desired frame rate of the first image.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: STMicroelectronics LtdInventors: Gilad Adler, Sason Sourani
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Publication number: 20180285225Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: STMicroelectronics International N.V.Inventors: Tejinder Kumar, Rakesh Malik
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Publication number: 20180287617Abstract: An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: STMicroelectronics International N.V.Inventors: Anand Kumar, Nitin Gupta, Nitin Jain
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Publication number: 20180284822Abstract: A low dropout regulator produces output at an intermediate node. A resistive divider is coupled between the intermediate node and ground and provides a feedback signal to the low dropout regulator. A transistor has a first conduction terminal coupled to the intermediate node and a second conduction terminal coupled to an output node. A first impedance is coupled to the output node, a first switch selectively couples the first impedance to a supply node, a second impedance coupled to the output node, and a second switch selectively couples the second impedance to a ground node. Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry switches the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: STMicroelectronics International N.V.Inventors: Kapil Kumar Tyagi, Nitin Gupta
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Publication number: 20180284192Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.Type: ApplicationFiled: March 29, 2017Publication date: October 4, 2018Applicant: STMicroelectronics, Inc.Inventors: Vinay Kumar, Pramod Kumar
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Publication number: 20180287379Abstract: Disclosed herein is an electronic device including an IO node, with a receiver coupled to receive input from the IO node. A transmitter driver has a first n-channel DMOS with a source coupled to the IO node. A pass gate circuit decouples the IO node from the receiver based upon presence of a negative voltage at the IO node and couples the IO node to the receiver based upon lack of presence of the negative voltage at the IO node. A transmit protection circuit applies the negative voltage from the IO node to the gate and bulk of the first n-channel DMOS based upon the presence of the negative voltage at the IO node.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: STMicroelectronics International N.V.Inventor: Ravinder Kumar
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Publication number: 20180287620Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal, and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: STMicroelectronics International N.V.Inventors: Gagan Midha, Kallol Chatterjee
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Publication number: 20180286763Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.Type: ApplicationFiled: April 1, 2018Publication date: October 4, 2018Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic GABEN
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Publication number: 20180286878Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.Type: ApplicationFiled: June 1, 2018Publication date: October 4, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Stephane Zoll, Philippe Garnier
