Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

Abstract: An embodiment circuit includes an operational amplifier having a first output terminal and a second output terminal. The circuit further includes a detector coupled between the first output terminal and the second output terminal of the operational amplifier. The detector is configured to detect a common-mode output voltage at the first output terminal and the second output terminal of the operational amplifier. The circuit also includes a feedback amplifier having a first input terminal coupled to the detector and a second input terminal configured to receive a reference voltage. The feedback amplifier is configured to generate a feedback signal based on the common-mode output voltage and the reference voltage and to provide the feedback signal to the operational amplifier. The circuit additionally includes an impedance element having a first terminal coupled to the first input terminal of the feedback amplifier and a second terminal coupled to a supply voltage.

Abstract: A source image is transformed into a destination image having a target aspect ratio. A reference region in the source image is defined. An extended region of interest of the source image having the target aspect ratio and containing the reference region is defined. A set of candidate image regions of increasing resolutions from the extended region of interest is determined, each having the target aspect ratio and containing the reference region. Candidate image regions are scaled to form a candidate target images. A quality metric is used to select a target image providing the best quality metric value.

Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.

Abstract: The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

Abstract: A multi-device module, comprising: a first substrate, which houses a first MEMS transducer, designed to transduce a first environmental quantity into a first electrical signal, and an integrated circuit, coupled to the first MEMS transducer for receiving the first electrical signal; a second substrate, which houses a second MEMS transducer, designed to transduce a second environmental quantity into a second electrical signal; and a flexible printed circuit, mechanically connected to the first and second substrates and electrically coupled to the integrated circuit and to the second MEMS transducer so that the second electrical signal flows, in use, from the second MEMS transducer to the integrated circuit.

Abstract: Disclosed herein is a touch screen controller for controlling touch sensing in a touch screen display, the touch screen display having a display layer controlled as a function of horizontal sync and vertical sync signals and a capacitive touch array comprised of drive lines and sense lines. The touch screen controller includes a driver and control circuitry. The control circuitry is configured to cause the driver to generate a driving signal on the drive lines during assertion of the horizontal sync signal, and cause the driver to generate the driving signal on the drive lines during assertion of the vertical sync signal. Analog touch sensing circuitry is configured to generate analog touch data as a function of signals on the sense lines resulting from generation of the drive signal on the drive lines.

Abstract: A method for real-time calibration of a gyroscope, configured for supplying a value of angular velocity that is function of a first angle of rotation about a first angular-sensing axis that includes defining a time interval, acquiring from an accelerometer an equivalent value of angular velocity that can be associated to the first angle of rotation; calculating a deviation between the value of angular velocity and the equivalent value of angular velocity; iteratively repeating the previous steps through the time interval, incrementing or decrementing an offset variable by a first predefined value on the basis of the values assumed by the deviations during the iterations, and updating the value of angular velocity as a function of the offset variable.

Abstract: An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.

Abstract: A circuit includes a multiplier, an adder, a first result register and a second result register coupled to outputs of the multiplier and the adder, respectively. The circuit further includes: a first selection unit configured to selectively provide, to the multiplier and in response to a first control signal, a first value from a first plurality of values; and a second selection unit configured to selectively provide, to the multiplier and in response to a second control signal, a second value from a second plurality of values. The circuit also includes: a third selection unit configured to selectively provide, to the adder and in response to a third control signal, a third value from a third plurality of values; and a fourth selection unit configured to selectively provide, to the adder and in response to a fourth control signal, a fourth value from a fourth plurality of values.

Abstract: An electronic device can be used for synchronizing tasks of an appliance that includes a memory access controller having inputs associated with priority levels. The device includes control circuits configured for receiving signals from events and delivering in response signals for activation of tasks. A configurable interface for external events designed to receive first event signals from at least one circuit of the appliance and to route some of them to the corresponding control circuits as a function of a first law of correspondence. A configurable interface for internal events designed to receive second event signals corresponding to the signals for activation of tasks and to route some of them to the control circuits as a function of a second law of correspondence.

Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

Abstract: A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.

Abstract: An integrated artificial neuron device includes a refractory circuit configured to inhibit signal integration for an inhibition duration after delivery of an output signal. The refractory circuit includes a first MOS transistor coupled between an input node and a reference node and having a gate connected to the output node by a second MOS transistor having a first electrode coupled to the supply node and a gate coupled to the output node. The refractory circuit further includes a resistive-capacitive circuit coupled between the supply node, the reference node and the gate of the second MOS transistor. An inhibition duration depends on a time constant of the resistive-capacitive circuit.

Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.