Patents Assigned to STMicroelectronics AS
  • INTEGRATED FUSE DEVICE
    Publication number: 20180254353
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Application
    Filed: September 14, 2017
    Publication date: September 6, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Multi-phase clock method and circuit for dynamic power control in a data processing pipeline
    Patent number: 10067550
    Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics (ALPS) SAS
    Inventor: Fabien Journet
  • Detection of disturbances of a power supply
    Patent number: 10067200
    Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventors: Bruno Leduc, Pascal Bernon, Stephane Clin
  • Macropixel processing system, method and article
    Patent number: 10068342
    Abstract: Digital image processing circuitry converts images in a color filter array (CFA) color space to images in a luminance-chrominance (YUV) 4:2:0 color space, and the images in the YUV 4:2:0 color space are processed by the digital image processing circuitry in the YUV 4:2:0 color space, for example, to apply noise filtering, etc. The converting includes simultaneously receiving pixel data defining a macro-pixel in the CFA color space. The processing in the YUV color space is applied on a macro-pixel level to the macro-pixel of the image in the YUV color space.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Mathieu Thivin, Stephane Drouard
  • Integrated circuit comprising at least an integrated antenna
    Patent number: 10068961
    Abstract: An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Another conductive structure extends in the peripheral portion on different planes of metallizations and forms a seal ring.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Pagani, Alessandro Finocchiaro
  • Method to form localized relaxed substrate by using condensation
    Patent number: 10068908
    Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Nicolas Loubet
  • Determining reflectance of a target using a time of flight ranging system
    Patent number: 10067223
    Abstract: An electronic device includes a ranging light source and a reflected light detector. A logic circuit causes the ranging light source to emit ranging light at a target. Reflected light from the target is detected using the reflected light detector, with the reflected light being a portion of the ranging light that reflects from the target back toward the reflected light detector. An intensity of the reflected light is determined using the reflected light detector. A distance to the target is determined based upon time elapsed between activating the ranging light source and detecting the reflected ranging light. Reflectance of the target is calculated, based upon the intensity of the reflected light and the distance to the target.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: September 4, 2018
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics, Inc.
    Inventors: Darin K. Winterton, Sam Lee
  • Self-supporting thin-film battery and method of manufacturing such a battery
    Patent number: 10069170
    Abstract: A self-supporting thin-film battery is manufacture by forming on the upper surface of a support substrate a vertical active stack having as a lower layer a metal layer having formed therein a first contact terminal of a first polarity of the battery and having formed therein as an upper layer a metal layer having a second contact terminal of a second polarity of the battery. A support film is then bonded to an upper surface of the upper layer. The lower layer is the separated from the substrate by projecting a laser beam through the substrate from a lower surface thereof to impinge on the lower layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Julien Ladroue, Mohamed Boufnichel
  • System and method for adjusting EEPROM write cycle duration according to supply voltage variation
    Patent number: 10068644
    Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Vertical power component
    Patent number: 10068999
    Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: September 4, 2018
    Assignees: STMICROELECTRONICS (TOURS) SAS, UNIVERSITE FRANCOIS RABELAIS
    Inventors: Samuel Menard, Gael Gautier
  • Method of manufacturing a waveguide
    Patent number: 10067291
    Abstract: A method of manufacturing a waveguide in a glass plate is disclosed. The glass plate is scanned with a laser beam directed orthogonally to the glass plate to form a trench according to a pattern of the waveguide to be formed. The scanning is performed by pulses of the laser beam having a duration between 2 and 500 femtoseconds. The glass plate with the trench is treated with hydrofluoric acid. After treating the glass plate, the trench is filled with a material having an index different from that of glass, and, after filling the trench, a cladding layer is deposited.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics SA
    Inventors: Cédric Durand, Frédéric Gianesello, Folly Eli Ayi-Yovo
  • Power component protected against overheating
    Patent number: 10069001
    Abstract: A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 4, 2018
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Samuel Menard
  • Sense amplifier for non-volatile memory devices and related methods
    Patent number: 10068643
    Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 4, 2018
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Marco Pasotti, Marcella Carissimi, Rajat Kulshrestha, Chantal Auricchio
  • Time to digital converter (TDC) with synchronous output and related methods
    Patent number: 10067224
    Abstract: A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, and provide a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: John Kevin Moore, Neale Dutton
  • HIGHER PIXEL DENSITY HISTOGRAM TIME OF FLIGHT SENSOR WITH HIGHER PIXEL DENSITY
    Publication number: 20180246212
    Abstract: A distance from an apparatus to at least one object is determined by generating a first signal and generating light modulated by the first signal to be emitted from the apparatus. Light reflected by the at least one object is detected using a Time-of-flight detector array, wherein each array element of the Time-of-flight detector array generates an output signal from a series of photon counts over a number of consecutive non-overlapping time periods. The output signals are compared to the first signal to determine at least one signal phase difference. From this at least one signal phase difference a distance from the apparatus to the at least one object is determined.
    Type: Application
    Filed: October 18, 2017
    Publication date: August 30, 2018
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventors: John Kevin Moore, Neale Dutton, Jeffrey M. Raynor
  • WAFER LEVEL PACKAGING, OPTICAL DETECTION SENSOR AND METHOD OF FORMING SAME
    Publication number: 20180248068
    Abstract: An optical detection sensor functions as a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. The sensor is formed by encapsulating the transmissive structure in a first encapsulant body and encapsulating the optical system in a second encapsulant body. The first and second encapsulant bodies are then joined together. In a wafer scale assembling the structure resulting from the joined encapsulant bodies is diced to form optical detection sensors.
    Type: Application
    Filed: May 3, 2018
    Publication date: August 30, 2018
    Applicant: STMicroelectronics Pte Ltd
    Inventors: Yonggang Jin, Wee Chin Judy Lim
  • MACH-ZEHNDER (MZ) RING OPTICAL MODULATOR
    Publication number: 20180246389
    Abstract: A Mach-Zehnder ring modulator includes a first optical path having a first diode and a optical path having a second diode. Each of the first and second diodes operates responsive to a voltage signal by modifying a phase of a light signal. A first optical coupler provides first and second light signals to the first and second optical paths, respectively. A second optical coupler couples outputs from the first and second optical paths. A feedback path is coupled between an output of the second optical coupler and an input of the first optical coupler.
    Type: Application
    Filed: August 17, 2017
    Publication date: August 30, 2018
    Applicant: STMicroelectronics SA
    Inventors: Valerie Danelon, Denis Pache, Christophe Arricastres
  • INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION
    Publication number: 20180247874
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Application
    Filed: October 3, 2017
    Publication date: August 30, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoît Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • INTEGRATED CIRCUIT WITH DETECTION OF THINNING VIA THE BACK FACE AND DECOUPLING CAPACITORS
    Publication number: 20180247901
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Application
    Filed: September 8, 2017
    Publication date: August 30, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Semiconductor electronic device with improved testing features and corresponding packaging method
    Patent number: 10062668
    Abstract: An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit and a respective top surface, which extends in a horizontal plane, and are stacked on one another in a vertical direction, transverse to the horizontal plane, and staggered parallel to the same horizontal plane. Provided at a first portion of the top surface is a first plurality of contact pads, and provided at a second portion of the top surface is a second plurality of contact pads. The first portion is covered by a overlying die, and the second portion is exposed and freely accessible. At least some of the contact pads of the first plurality are electrically coupled to internal through silicon vias traversing a substrate of the overlying die to put overlapping dies in electrical contact.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 28, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Pagani