Abstract: An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.

Abstract: An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.

Abstract: A method for forming a molded proximity sensor with an optical resin lens and the structure formed thereby. A light sensor chip is placed on a substrate, such as a printed circuit board, and a diode, such as a laser diode, is positioned on top of the light sensor chip and electrically connected to a bonding pad on the light sensor chip. Transparent, optical resin in liquid form is applied as a drop over the light sensor array on the light sensor chip as well as over the light-emitting diode. After the optical resin is cured, a molding compound is applied to an entire assembly, after which the assembly is polished to expose the lenses and have a top surface flush with the top surface of the molding compound.

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.

Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.

Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract: A photodiode structure is based on the use of a double junction sensitive to different wavelength bands based on a magnitude of a reverse bias applied to the photodiode. The monolithic integration of a sensor with double functionality in a single chip allows realization of a low cost ultra-compact sensing element in a single packaging useful in many applications which require simultaneous or spatially synchronized detection of optical photons in different spectral regions.

Abstract: A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

Abstract: An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.

Abstract: A network services provider grants a subscription to a user for use of mobile network services to communicate voice, data, and text information with a specific mobile device. Mobile devices store one or more subscriptions, each of which may be activated. An activated subscription stored in the mobile device is now made portable. The user wants to pass the portable subscription from a first mobile device to a second mobile device. The user forms a first communicative relationship between the first mobile device and a second mobile device and receives from the second mobile device identification information associated with the second mobile device. The first mobile device passes the identification information to the network services provider and receives a confirmation. The user forms a second communicative relationship between the first mobile device and the second mobile device, and the second mobile device confirms activation of the portable subscription.

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract: A probe card is adapted for testing at least one integrated circuit that integrated on a corresponding at least one die of a semiconductor material wafer. The probe card includes a board adapted for the coupling to a tester apparatus. Several probes are coupled to the board. The probe card includes replaceable elementary units, wherein each unit includes at least one probe for contacting externally-accessible terminals of an integrated circuit under test. The replaceable elementary units are arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract: A driving apparatus configured to drive a light emitting device includes a driving current source module operable to supply current to the light emitting device via a node during operation. A protection module coupled to the node and the driving current source module selectively injects current to the node during operation. The driving current source module is controlled based on a detection result of a voltage on the node.

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.

Abstract: An integrated circuit includes an IO node, and an IO driver coupled thereto. The IO driver has a first driving circuit with a first PMOS transistor having a source coupled to a supply node and a gate coupled to receive a PMOS driving signal, and a first NMOS transistor having a source coupled to ground, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to receive a NMOS driving signal. The IO driver also has a second driving circuit with a second PMOS transistor having a source coupled to the supply node and a gate coupled to receive a first delayed version of the PMOS driving signal, and a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a source coupled to ground, and a gate coupled to receive a first delayed version of the NMOS driving signal.