Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

Abstract: A circuit is for balancing currents flowing through a parallel assembly of semiconductor components of the same type. The circuit may include a respective regulation circuit for each semiconductor component. Each regulation circuit may include a comparator of a first signal representative of the current flowing through the component with a reference signal, and a resistive element of a changeable resistance and controlled by the comparator.

Abstract: A method can be used to generate a reference clock signal having a reference frequency. N clock sub-signals are generated, where N is greater than or equal to 2. The N clock sub-signals are successively mutually shifted out of phase by ?/N and each clock sub-signal has an elementary frequency that is equal to the reference frequency divided by N. The N clock sub-signals are propagated over propagation paths. The elementary frequency and a length of the longest propagation path are chosen so that each sub-signal has an acceptable degree of deformation. The duration of each sub-signal edge is longer than quarter of the period of the reference frequency. The reference clock signal is generated by EXCLUSIVE OR combining the propagated clock sub-signals at the end of their respective propagation paths.

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract: A method and apparatus for capturing stable images are disclosed. An ambient light sensor makes measurements of ambient light. A change in ambient light between two measurements is determined. If the change in ambient light measurements falls in a predefined range, then the change may be attributable to ambient light sensor being blocked by a user to trigger image capturing. Consequently, a camera is triggered to capture an image. Conversely, if the change in ambient light measurement is outside the range, image capturing is not triggered as the change may be attributable to other factors.

Abstract: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.

Abstract: A pressure sensor device is to be positioned within a material where a mechanical parameter is measured. The pressure sensor device may include an IC having a ring oscillator with an inverter stage having first doped and second doped piezoresistor couples. Each piezoresistor couple may include two piezoresistors arranged orthogonal to one another with a same resistance value. Each piezoresistor couple may have first and second resistance values responsive to pressure. The IC may include an output interface coupled to the ring oscillator and configured to generate a pressure output signal based upon the first and second resistance values and indicative of pressure normal to the IC.

Abstract: An energy harvester circuit operates to harvest energy in battery-less electrical apparatus. The circuit includes a string of capacitors coupled to a circuit input to receive energy to be harvested. A string of transistors are coupled as pumping transistors to respective ones of the capacitors in the string of capacitors. A compensation coupling circuit is coupled between each transistor in the string of pumping transistors and one of a subsequent or a preceding transistor in the string of pumping transistors.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

Abstract: A battery structure has structure anode and cathode contacts on a front face and on a rear face. The battery structure includes a battery having battery anode and cathode contacts only on a front face thereof. A film including a conductive layer and an insulating layer jackets the battery. The conductive layer extends over the battery anode and cathode contacts and is interrupted therebetween. Openings are provided in the insulating layer on the front and rear faces of the battery structure to form the structure anode and cathode contacts of the battery structure.

Abstract: A case includes a base for receiving a portable phone and a flap hinged to the base and including a housing configured to receive a microcircuit card. A first contactless communication antenna is provided in the flap for coupling to an antenna of the microcircuit card. A second contactless communication antenna is provided in the base for coupling to an antenna of the portable phone. The first and second first contactless communication antennae are electrically connected to each other.

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: A charge pump circuit can be controlled by a control signal that is generated from a first signal coming from and output signal of the charge pump circuit, from a reference signal, and from a clock signal. The generation of the control signal includes a comparison of the reference signal and of the first signal in tempo with a timing signal coming from the clock signal.

Abstract: An optical electronic device may include a plurality of different optical sources, and a global shutter sensor including an array of global shutter pixels, with each global shutter pixel including a plurality of storage elements. A controller may be coupled to the plurality of optical sources and the global shutter sensor and configured to cause a first optical source to illuminate and a first storage element in each global shutter pixel to store optical data during a first integration period, cause a second optical source to illuminate and a second storage element in each global shutter pixel to store optical data during a second integration period, and output the stored optical data from the first and second storage elements of the global shutter pixels after the first and second integration periods.

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.