Abstract: Disclosed herein is an electronic device that includes a peak detection circuit configured to receive a mirror sense signal from an oscillating mirror and to generate peak information for a mirror period as a function thereof. The electronic device includes a mirror control circuit that estimates an opening angle of the oscillating mirror as a function of the peak information, generates a control signal for the oscillating mirror as a function of the estimated opening angle, and resets the peak detection circuit at an end of the mirror period.

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

Abstract: The following steps are performed in connection with a photodiode circuit: a) resetting the photodiode circuit; b) determining when a photodiode voltage changes in response to illumination to reach a threshold; and c) updating a counter in response to the determination in step b). The steps a) to c) are repeated until an end of a measurement period is reached. The value of the counter at the end of the measurement period is then output to indicate an intensity of the illumination.

Abstract: A touch screen controller disclosed herein includes a circuit configured to generate a digital touch voltage comprises of samples, at a base sampling rate. The touch screen controller also includes a digital processing unit configured to analyze a first subset of samples of the digital touch voltage samples to determine noise content thereof, the first subset of samples corresponding to samples at a first investigated sampling rate that is a first function of the base sampling rate. The digital processing unit is also configured to analyze a second subset of samples of the digital touch voltage to determine noise content thereof, with the second subset of samples corresponding to samples at a second investigated sampling rate that is a second function of the base sampling rate, and determine a preferred sampling rate from among the first and second investigated sampling rates as a function of determined noise content thereof.

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

Abstract: A switch includes three components. Each component includes a stack of three semiconductor regions of alternating conductivity types and a control region in a first of the three semiconductor regions having a type opposite to that of the first semiconductor region. The first semiconductor regions of the first and second components are of a same conductivity type and the first semiconductor regions of the first and third components are of opposite conductivity types. The first semiconductor region of the first component is connected to the control regions of the second and third components. The first semiconductor regions of the second and third components are connected to a first switch terminal, the third semiconductor regions of the first, second, and third components are connected to a second switch terminal, and the control region of the first component is connected to a third switch terminal.

Abstract: An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract: An electronic device includes first and second terminals with an electronic circuit coupled there between. The electronic circuit includes a protection circuit and a resistive-capacitive circuit. The resistive-capacitive circuit triggers the protection circuit to protect against electrostatic discharges in the presence of a current pulse between the first and second terminals. A control circuit is configured to slow down a discharge from the resistive-capacitive circuit when the protection circuit is triggered.

Abstract: A method for touch screen self-capacitance foreign matter detection for a capacitive touch screen is disclosed. By iteratively performing methods of self-capacitance scanning and foreign matter scanning foreign matter may be detected.

Abstract: A photodetector is formed in a silicon-on-insulator (SOI) type semiconductor layer. The photodetector includes a first region and a second region of a first conductivity type separated from each other by a central region of a second conductivity type so as to define a phototransistor. A transverse surface of the semiconductor layer is configured to receive an illumination. The transverse surface extends orthogonally to an upper surface of the central region.

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.

Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.

Abstract: A circuit may include a first circuit configured to generate a voltage signal for generating an optical pulse, the voltage signal being generated based on a phase control signal, and an array of single photon avalanche diode (SPAD) cells configured to detect a phase of the optical pulse. The circuit may include a phase control circuit configured to generate the phase control signal based upon a target phase value and the detected phase of the optical pulse.

Abstract: An image sensor including: a plurality of pixels each including a photodiode coupled to first and second capacitive elements by first and second transistors; a control circuit provided to acquire, for each pixel, a first and second value V_S and V_M representative of illumination levels of the photodiode during the first second periods, the first period being divided into a plurality of first sub-periods and the second period being divided into a plurality of second sub-periods, the first and second sub-periods sub-periods being interlaced; and a sum circuit capable of calculating, for each pixel, a value V_MS=C_S*V_S+C_M*V_M, C_S et C_M being first and second coefficients such that values C_S*V_S and C_M*V_M are substantially equal when the illumination of the photodiode is continuous.

Abstract: A method can be used for contactless communication of an object with a reader using active load modulation. A main clock signal is generated within the object. The generating includes a calibration phase and a transmission phase. The calibration phase includes locking an output signal of a controlled main oscillator onto a phase and frequency of a secondary clock signal received from the reader and estimating a frequency ratio between a frequency of the output signal of the main oscillator and a reference frequency of a reference signal originating from a reference oscillator. The transmission phase includes only frequency-locking the output signal of the main oscillator onto the frequency of the reference signal corrected by the estimated frequency ratio.

Abstract: An apparatus for actuating in rotation and reading a centrifugal microfluidic disk for biological and/or biochemical analyses, comprising: a container body, defining an internal chamber forming a closed curvilinear path, the path comprising a housing region configured to house the centrifugal microfluidic disk, and a curvilinear channel fluidically coupled to the housing region; a heater operatively arranged in a section of the curvilinear channel; and a fan operatively arranged in a respective section of the curvilinear channel.

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

Abstract: One or more embodiments disclosed herein are directed to a chip scale package camera module that includes a glass interposer between a lens and an image sensor. In some embodiments, the glass interposer is made from one or more layers of optical quality glass and includes an infrared filter coating. The glass interposer also includes electrically conductive paths to connect the image sensor, mounted on one side of the glass interposer, with other components such as capacitors, which may be mounted on a different side of the glass interposer, and the rest of the camera system. The conductive layers include traces and vias that are formed in the glass interposer in areas away from the path of light in the camera module, such that the traces and vias do not block the light between the lens and the image sensor.