Abstract: A projective MEMS device, including: a fixed supporting structure made at least in part of semiconductor material; and a number of projective modules. Each projective module includes an optical source, fixed to the fixed supporting structure, and a microelectromechanical actuator, which includes a mobile structure and varies the position of the mobile structure with respect to the fixed supporting structure. Each projective module further includes an initial optical fiber, which is mechanically coupled to the mobile structure and optically couples to the optical source according to the position of the mobile structure.

Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.

Abstract: A first closed enclosure defines a cavity having an inner dimension smaller than 5 mm. At least one second resiliently deformable closed enclosure is connected in fluid communication with the first enclosure. A fluid at more than 90% in the liquid state fills the first and second enclosures. A first portion of the first enclosure is in contact with a hot source of a temperature higher than the evaporation temperature of the fluid. A second portion of the first enclosure located between the first portion and the resiliently deformable closed enclosure is in contact with a cold source at a temperature lower than the condensation temperature of the fluid. An electromechanical transducer is coupled to a deformable membrane of the resiliently deformable closed enclosure.

Abstract: A circuit includes a final stage that includes an H-bridge comprising first and second half-bridges. A read circuit is configured to read a load current supplied by a class-D audio-amplifier to a load. The read circuit is configured for estimating the load current by reading a current at an output by the first or second half-bridge by measuring a drain-to-source voltage during an ON period of a power transistor of the H-bridge. A sensing circuit is configured to detect a first drain-to-source voltage from a transistor of the first half-bridge and a second drain-to-source voltage from a corresponding transistor of the second half-bridge. The sensing circuit is also configured to compute a difference between the first drain-to-source voltage and the second drain-to-source voltage and to perform an averaging operation on the difference to obtain a sense voltage value to be supplied to an analog-to-digital converter.

Abstract: A radio or power transfer antenna, in the form of a planar conductive winding, with one of two ends of the planar conductive winding directly connected to a metal section or plane which continuously surrounds the planar conductive winding.

Abstract: A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.

Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.

Abstract: A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

Abstract: A method for manufacturing a cover for an electronic package includes placing an electrically conductive insert (including an electrical contact surface) inside a cavity of a mold in a position such that the electrical contact surface is in contact with a face of the cavity of the mold. A coating material is injected into said cavity and set so as to produce a substrate that is overmolded around the insert and forms the cover where the electrical contact surface of the overmolded substrate is not covered by the coating material. An electronic package is then formed from a chip mounted on a carrier substrate that is covered by the cover. The electrical contact surface is located above and electrically connected to an electrical connection pad of either the chip or the carrier substrate.

Abstract: Disclosed herein is a touch screen controller operable with a touch screen. The touch screen controller includes input circuitry configured to receive touch data from the touch screen, and processing circuitry. The processing circuitry is configured to identify an island in the touch data, determine whether a horizontal groove is present in the island, determine whether a vertical groove is present in the island, and determine whether a diagonal groove is present in the island. The processing circuitry determines the island to indicate a single elongated touch where a diagonal groove is present in the island but horizontal and vertical grooves are not present in the island.

Abstract: A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.

Abstract: An electronic device includes a support plate having a mounting face. An electronic chip has a front face mounted on the mounting face of the support plate. A rear face of the electronic chip located opposite to the front face is provided with rear grooves that define, between the grooves, rear zones. A rear layer made of a heat-conducting material is spread over the rear face of the electronic chip so as to at least partly cover the rear zones and at least partially fill the rear grooves.

Abstract: An AC/DC converter includes: a first terminal and a second terminal for receiving an AC voltage and a third terminal and a fourth terminal for supplying a DC voltage. A rectifying bridge includes input terminals respectively coupled to the first terminal and the second terminal, and output terminals respectively coupled to the third terminal and fourth terminal. A first branch of the rectifying bridge includes, connected between the output terminals, two series-connected thyristors with a junction point of the two thyristors being connected to a first one of the input terminals. A second branch of the rectifying bridge is formed by series connected diodes. A control circuit is configured to generate control signals for application to the control gates of the thyristors.

Abstract: A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.

Abstract: Embodiments of the present disclosure include a system and a method of accessing a system. An embodiment is a system including an imaging system including a controller and a first camera, the controller having a communication connection configured to transmit or receive content or control signals, and a mobile device including a second camera, the mobile device having a communication interface configured to transmit or receive content or control signals with the controller, the controller being configured to compare images from the first and second cameras to allow access to the controller from the mobile device.

Abstract: An integrated electronic device includes a substrate having an opening extending therethrough. The substrate includes an interconnection network, and connections coupled to the interconnection network. The connections are to be fixed on a printed circuit board. An integrated photonic module is electrically connected to the substrate, with a portion of the integrated photonic module in front of or overlapping the opening of the substrate. An integrated electronic module is electrically connected to the photonic module, and extends at least partly into the opening of the substrate. The electronic module and the substrate may be electrically connected onto the same face of the photonic module.

Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).