Patents Assigned to STMicroelectronics AS
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Patent number: 9954519Abstract: A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.Type: GrantFiled: July 20, 2017Date of Patent: April 24, 2018Assignee: STMicroelectronics S.r.l.Inventors: Marco Terenzi, Davide Ugo Ghisu
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Patent number: 9952094Abstract: A semiconductor device for flame detection, including: a semiconductor body having a first conductivity type conductivity, delimited by a front surface and forming a cathode region; an anode region having a second conductivity type conductivity, which extends within the semiconductor body, starting from the front surface, and forms, together with the cathode region, the junction of a photodiode that detect ultraviolet radiation emitted by the flames; a supporting dielectric region; and a sensitive region, which is arranged on the supporting dielectric region and varies its own resistance as a function of the infrared radiation emitted by the flames.Type: GrantFiled: December 12, 2016Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Massimo Cataldo Mazzillo, Antonella Sciuto
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Patent number: 9954501Abstract: An amplifier includes a first input branch and a second input branch that form a differential input stage and a current mirror connected to the differential input. The current mirror is governed as a function of a common mode feedback signal applied to a control node of the current mirror. A second, amplification, stage includes a branch flowing through which is a current, which is a function of the current that flows in the first input branch, and is in turn connected to a first output branch. A capacitive element is coupled between the control node and the second stage. The circuit is symmetrical with respect to the input stage.Type: GrantFiled: May 16, 2016Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Garbarino, Roberto Modaffari, Germano Nicollini
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Patent number: 9954079Abstract: Methods form an electronic semiconductor device that includes a body having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side. A body region extends in the second structural region at the first side. A source region extends inside the body region and a lightly-doped drain region faces the first side of the body. A gate electrode is formed over the body region. A trench dielectric region extends through the second structural region in a first trench conductive region immediately adjacent to the trench dielectric region. A second trench conductive region is in electrical contact with the body region and source region. An electrical contact on the body is in electrical contact with the drain region through the first structural region.Type: GrantFiled: December 9, 2015Date of Patent: April 24, 2018Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Cascino, Leonardo Gervasi, Antonello Santangelo
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Patent number: 9953983Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.Type: GrantFiled: April 7, 2017Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS, INC.Inventor: John H. Zhang
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Patent number: 9954445Abstract: A control circuit controls a switch of a switching current converter receiving an input quantity, with a transformer having a primary winding and a sensor element generating a sensing signal correlated to a current in the primary winding. The control circuit has a comparator stage configured to compare a reference signal with a comparison signal correlated to the sensing signal and generate an opening signal for the switch. The comparator stage has a comparator element and a delay-compensation circuit. The delay-compensation circuit is configured to generate a compensation signal correlated to the input quantity and to a propagation delay with respect to the opening signal. The comparator element generates the opening signal with an advance correlated to the input quantity and to the propagation delay.Type: GrantFiled: November 23, 2015Date of Patent: April 24, 2018Assignee: STMicroelectronics S.r.l.Inventor: Giovanni Gritti
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Patent number: 9952291Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.Type: GrantFiled: April 29, 2016Date of Patent: April 24, 2018Assignee: STMicroelectronics S.r.l.Inventors: Marco Crescentini, Marco Tartagni, Aldo Romani, Roberto Canegallo, Marco Marchesi, Domenico Cristaudo
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Patent number: 9954119Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.Type: GrantFiled: January 10, 2017Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Roberto Simola, Pascal Fornara
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Patent number: 9952445Abstract: Various embodiments provide an optical image stabilization circuit that synchronizes its gyroscope and drive circuit using gyroscope data ready signals and gyroscope reset signals. In response to a gyroscope data ready signal, the optical image stabilization circuit synchronously obtains position measurements of a camera lens when power drive signals are not transitioning from one power level to another power level, and synchronously transitions the power drive signals simultaneously with gyroscope reset signals. By synchronizing the gyroscope and the drive circuit, the gyroscope and other onboard sensing circuits are isolated from noise generated by the drive circuit.Type: GrantFiled: October 22, 2015Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS, INC.Inventors: Chih-Hung Tai, Felix Kim, Mark A. Lysinger
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Patent number: 9953837Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.Type: GrantFiled: March 26, 2015Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Pierre Caubet, Sylvain Baudot
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Patent number: 9954434Abstract: A controller for a multiphase converter comprises a first stage controller for producing a first gate drive signal to turn on a first power transistor of a first boost converter; a delay element configured to produce a delayed signal by delaying the first gate drive signal by half a cycle length; a time difference detection element configured to: output a turn on command based on a zero crossing detection (ZCD) signal indicating that one or more zero current conditions of a second boost converter of the multiphase converter are met and the delayed signal; and a second stage controller configured to assert a second gate drive signal to turn on a second power transistor of the second boost converter based on the turn on command.Type: GrantFiled: June 26, 2017Date of Patent: April 24, 2018Assignee: STMicroelectronics S.r.l.Inventors: Alberto Bianco, Giuseppe Scappatura
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Patent number: 9950511Abstract: One or more embodiments are directed to a microfluidic assembly that includes an interconnect substrate coupled to a microfluidic die. In one embodiment, the microfluidic die includes a ledge with a plurality of bond pads. The microfluidic assembly further includes an interconnect substrate having an end resting on the ledge proximate the bond pads. In another embodiment, the interconnect substrate abuts a side surface of the ledge or is located proximate the ledge. Conductive elements couple the microfluidic die to contacts of the interconnect substrate. Encapsulant is located over the conductive elements, the bond pads, the contacts.Type: GrantFiled: September 27, 2016Date of Patent: April 24, 2018Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS (MALTA) LTDInventors: Simon Dodd, Ivan Ellul, Christopher Brincat
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Publication number: 20180109294Abstract: A system includes an antenna, and communications circuitry coupled to the antenna and configured for at least one of receiving and transmitting information via the antenna based on a contactless communications protocol. A charger is configured for contactless charging a power supply module via the antenna. A controller is configured for selectively operating the communications circuitry and the charger.Type: ApplicationFiled: December 18, 2017Publication date: April 19, 2018Applicant: STMicroelectronics (Rousset) SASInventors: Pierre Rizzo, Anthony TORNAMBE
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Publication number: 20180108762Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.Type: ApplicationFiled: December 13, 2017Publication date: April 19, 2018Applicant: STMicroelectronics SAInventor: Pascal Chevalier
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Publication number: 20180106854Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Applicant: STMicroelectronics S.r.l.Inventor: Alberto Pagani
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Publication number: 20180107340Abstract: A method of compensated touch data values disclosed herein includes acquiring touch data values about a dead sensing zone of a touch screen, and determining a peak value of those touch data values. Then, a new peak value is calculated as a function of an average of the peak value and another value of the touch data value, and a sharpness value for the dead sensing zone is generated if a second highest value of the touch data values is less than the new peak value. Thereafter, compensated touch data values are generated for the dead sensing zone if the second highest value is greater than the new peak value.Type: ApplicationFiled: December 19, 2017Publication date: April 19, 2018Applicant: STMicroelectronics Asia Pacific Pte LtdInventors: Rooney Kim, Lokesh Kumar Korapati
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Publication number: 20180108766Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.Type: ApplicationFiled: December 7, 2017Publication date: April 19, 2018Applicant: STMicroelectronics (Tours) SASInventor: Samuel Menard
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Patent number: 9947612Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.Type: GrantFiled: December 3, 2015Date of Patent: April 17, 2018Assignee: STMICROELECTRONICS, INC.Inventors: Jefferson Talledo, Rammil Seguido
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Patent number: 9948253Abstract: A push-pull amplifier includes a pair of active devices driving the primary side of a double distributed active transformer (DDAT). The primary side of the DDAT includes a cascaded arrangement of primary windings of a first set of transformers with the active devices coupled ends of cascaded arrangement of primary windings. The secondary side of the DDAT includes a cascaded arrangement of secondary windings of a second set of transformers coupled to a load. Secondary windings of the first set of transformers drive inputs of respective active stages. Outputs of the active stages drive respective primary windings of the second set of transformers.Type: GrantFiled: May 18, 2016Date of Patent: April 17, 2018Assignee: STMicroelectronics S.r.l.Inventor: Andrea Pallotta
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Patent number: 9948190Abstract: A power control module for an electronic converter is disclosed. The electronic converter includes a power stage comprising two input terminals for receiving a first power signal and two output terminals for providing a second power signal. The electronic converter includes, moreover, a control circuit configured to control operation of the power stage as a function of a feedback control signal. In particular, the power control module includes a pre-elaboration module configured to generate a reference signal as a function of the feedback control signal and a first signal being representative of a voltage applied to the two input terminals. An error amplifier is configured to generate a modified control signal as a function the reference signal and a second signal being representative of a current flowing through the two input terminals.Type: GrantFiled: May 27, 2016Date of Patent: April 17, 2018Assignee: STMicroelectronics S.r.l.Inventor: Claudio Adragna