Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor a varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

Abstract: A sensing apparatus includes a sensor and a processor. The sensor includes at least one light sensitive detector. The processor determines a first control value to control a voltage differential across the at least one light sensitive detector, and compares the first control value with a reference value associated with a reference temperature. Based on the comparison, the processor provides adjustment information for adjusting at least one output of the sensing apparatus, and an operating parameter of the sensing apparatus other than the voltage differential.

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

Abstract: The present disclosure is directed to a microfluidic die that includes ejection circuitry and one time programmable memory with a minimal number of contact pads to external devices. The die includes a relatively large number of nozzles and a relatively small number of contact pads. The die includes decoding circuitry that utilizes the small number of contact pads to control the drive and ejection of the nozzles and the reading/writing of the memory with the same contact pads.

Abstract: A time of flight detector includes an electromagnetic radiation emitter configured to emit a beam of radiation. A first optical element receives the beam of radiation and generates a collimated beam of radiation. A second optical element defines a narrow imaging field of view sufficient to capture reflected electromagnetic radiation from the collimated beam. An electromagnetic radiation sensor then senses the captured reflected electromagnetic radiation from the collimated beam in the narrow imaging field of view. Further narrowing of the imaging field of view is accomplished by selective enabling a sub-array of photosensitive elements with the electromagnetic radiation sensor.

Abstract: Embodiments of the present disclosure include a method of operating an arc fault detection system, an arc fault detection system, and a system. An embodiment is a method of operating an arc fault detection system coupled to a power line, the method including determining one or more arc fault detection windows in power line signals on the power line, the power line signals comprising a communication signal and an alternating current (AC) power signal. The method further includes receiving the power line signals from the power line during the one or more arc fault detection windows, and performing arc fault detection processing on the received power line signals.

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

Abstract: Method for the estimation of the heart-rate using photoplethysmography on a body organ, for example a wrist of a user, comprising acquiring optically from said body organ a heart beat signal, acquiring an acceleration signal representative of the acceleration of said body organ, selecting data blocks of said acquired heart beat signal and acceleration signal, compensating said heart beat signal by the acceleration signal, calculating the heart rate value on the basis of said compensated heart beat signal.

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.

Abstract: A color calibration device for a laser scanning apparatus includes a compensation unit configured to electronically compensate for positional errors of the three-color laser source. The compensation unit includes an emitted light detector configured to measure a power of an emitted light beam. A calibration unit coupled to the emitted light detector has a controller configured to generate a quantity correction value for the three-color laser source. A laser source control element is configured to generate a control quantity for the three-color laser source, based on the quantity correction value. A dominant color detector is configured to detect any dominant color in the light beam being projected and actuate the controller for the dominant color.

Abstract: An electronic device includes an antenna, an irremovable component, a removable component, an impedance matching circuit, and a controller. The impedance matching circuit is arranged in a first configuration corresponding to the removable component connected to the irremovable component. The impedance matching circuit has a first capacitor, a second capacitor, and a third capacitor. The controller is configured to arrange the impedance matching circuit in a second configuration corresponding to the removable component being disconnected from the irremovable component.

Abstract: An assembly includes an integrated circuit chip and a plate with at least one heat removal channel arranged between the chip and the plate. Metal sidewalls are formed to extend from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate.

Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.