Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract: According to an embodiment, a voltage regulator includes a linear voltage regulator (LVR) and a transient feedback circuit. The LVR a primary feedback loop, an input terminal configured to receive an input voltage, and an output terminal configured to output a regulated voltage. The transient feedback circuit is coupled to the output terminal and the primary feedback loop, and is configured to provide a first current with a first polarity to the primary feedback loop when current flowing through the output terminal is increasing.

Abstract: An RFID transponder device has antenna terminals for coupling an antenna system to the device. A transmitter and a receiver are coupled to the antenna terminals. The device has at least one damping resistance connected to at least one of the antenna terminals. The at least one damping resistance is connected, depending on a voltage swing at the antenna terminals during a transmission burst period, either together with a serially connected switch in parallel to the antenna terminals that are coupled to the receiver, or together with a parallel connected switch between one of the antenna terminals and a terminal of the transmitter. A damping control is configured to activate the at least one damping resistance during a damping period after the transmission burst period by controlling the respective switch.

Abstract: An embodiment in a single structure combines a pad comprising a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside the chip itself and at least one inductor that can be used to receive/transmit electromagnetic waves or to supply the chip with power or both. By combining a connection pad and an inductor in a single structure, it is possible to reduce the overall area that otherwise would be occupied exclusively by the inductors, thus reducing the cost and size of integrated circuits that include such a structure.

Abstract: A fail-safe device may be coupled to a main device for actuating a switch responsive to a failure. The fail-safe device may include a fail-safe circuit, and an isolation trench surrounding the fail-safe circuit and isolating the fail-safe circuit from the main device. The fail-safe device may include an internal power supply connection, an internal reference voltage connection, a self-biased drive block configured to drive the at least one switch, and a receiver configured to receive failure signals from the main device.

Abstract: The following steps are performed in connection with a photodiode circuit: a) resetting the photodiode circuit; b) determining when a photodiode voltage changes in response to illumination to reach a threshold; and c) updating a counter in response to the determination in step b). The steps a) to c) are repeated until an end of a measurement period is reached. The value of the counter at the end of the measurement period is then output to indicate an intensity of the illumination.

Abstract: Photoluminescence from a sample detector is detected using an array of photo-sensitive detectors. At least one first photo-sensitive detector of the array is provided with a first type of linear polarization filter and at least one second photo-sensitive detector is provided with a second type of linear polarization filter. The first type of linear polarization filter has a plane of polarization which is at angled with respect to a plane of polarization of said second type of polarization filter.

Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.

Abstract: A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.

Abstract: A first resistor and a second resistor are coupled in series between a voltage source and an active load. When the current drawn by the active load exceeds a current threshold corresponding to a maximum admissible voltage drop across the first resistor, a stabilization current is delivered to the node common to the series coupled first and second resistors in such a way as to stabilize the voltage on the terminals of the active load at a threshold value. In the presence of such a current in excess of the current threshold, the current consumed by the active load is measured from the voltage drop across the second resistor. Conversely, if the current is less than the current threshold, the current consumed by the active load is measured from the voltage drop across the first resistor.

Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

Abstract: An electronic device may include a transducer configured to generate an electrical output responsive to an input, and a data storage element configured to change state responsive to the transducer. The electronic device may include a power circuit configured to turn on and supply power responsive to the data storage element changing state, and a processing circuit configured to be powered by the power circuit.

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

Abstract: A sequence of images is processed to generate optical flow data including a list of motion vectors. The motion vectors are grouped based on orientation into a first set of moving away motion vectors and a second set of moving towards motion vectors. A vanishing point is determined as a function of the first set of motion vectors and a center position of the images is determined. Pan and tilt information is computed from the distance difference between the vanishing point and the center position. Approaching objects are identified from the second set as a function of position, length and orientation, thereby identifying overtaking vehicles. Distances to the approaching objects are determined from object position, camera focal length, and pan and tilt information. A warning signal is issued as a function of the distances.

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

Abstract: A sequence of images obtained by a camera mounted on a vehicle is processed in order to generate Optical Flow data including a list of Motion Vectors being associated with respective features in the sequence of images. The Optical Flow data is analyzed to calculate a Vanishing Point by calculating the mean point of all intersections of straight lines passing through motion vectors lying in a road. An Horizontal Filter subset is determined taking into account the Vanishing Point and a Bound Box list from a previous frame in order to filter from the Optical Flow the horizontal motion vectors. The subset of Optical Flow is clustered to generate the Bound Box list retrieving the moving objects in a scene. The Bound Box list is sent to an Alert Generation device and an output video shows the input scene where the detected moving objects are surrounded by a Bounding Box.

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

Abstract: A three dimensional (3D) device is formed from a first level and a second level that are attached together. The first level includes a backside illuminated two dimensional (2D) image sensor including an array of first pixels sensitive to visible light. The second level includes a frontside illuminated depth sensor including an array of second pixels sensitive to near infrared light. The first and second levels are attached in a manner such that radiation, in particular the near infrared light, received at the backside of the first level passes through the first level to reach the depth sensor in the second level.

Abstract: An integrated image sensor with backside illumination includes a pixel. The pixel is formed by a photodiode within an active semiconductor region having a first face and a second face. A converging lens, lying in front of the first face of the active region, directs received light rays towards a central zone of the active region. At least one diffracting element, having a refractive index different from a refractive index of the active region, is provided at least partly aligned with the central zone at one of the first and second faces.

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.