Abstract: An electronic device disclosed herein includes a display layer generating display noise based on scanning thereof, and a sensing layer including a plurality of sense lines. A common voltage layer is coupled to the display layer and the sensing layer, with the common voltage layer capacitively coupling the display noise from the display layer to the each of the plurality of sense lines of the sensing layer via a different parasitic impedance. An amplitude of the display noise seen at an input to each sense line is a function of a location of that sense line. The electronic device includes a plurality of compensation impedances, with each compensation impedance coupled to a different one of the plurality of sense lines. Each of the plurality of compensation impedances has an impedance value such that an amplitude of the display noise at an output of each sense line is substantially equal.

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

Abstract: A transfer gate transistor includes a semiconductor substrate including a charge collection source region, a portion forming a channel region and a top region forming a drain region. A trench in the substrate surrounds the top region and the portion of the substrate. A vertical insulated gate structure for the transistor is formed in the trench. The vertical insulated gate structure includes an insulating liner on sidewalls and a bottom of said trench and an electrode including an upper conductive part and a lower conductive part. A width of the upper conductive part parallel to an upper surface of the substrate increases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the upper conductive part decreases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the lower conductive part is substantially constant.

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

Abstract: A microchip has a rear face attached to a front mounting face of a support plate. An encapsulation cover for the microchip is mounted to the support plate. The encapsulation cover includes a front wall, a peripheral wall extending from the front wall and an inside partition extending from the front wall and between opposite sides of the peripheral wall. The inside partition passes locally above the microchip to delimit two cavities. A bonding material is interposed between encapsulation cover and the support plate and microchip. An end part of the inside partition of the cover, adjacent to the front face of the microchip, include an accumulation and containment recess that is configured to at least partly receive the bonding material.

Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.

Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

Abstract: A MEMS device includes a fixed structure and a mobile structure with a reflecting element coupled to the fixed structure through at least a first deformable structure and a second deformable structure. Each of the first and second deformable structures includes a respective number of main piezoelectric elements, with the main piezoelectric elements of the first and second deformable structures configured to be electrically controlled for causing oscillations of the mobile structure about a first axis and a second axis, respectively. The first deformable structure further includes a respective number of secondary piezoelectric elements configured to be controlled so as to vary a first resonance frequency of the mobile structure about the first axis.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: A sensing device includes a barometric sensor, e.g., MEMS-based, and a processing unit coupled to the barometric sensor to receive therefrom a barometric signal. The processing unit is configured as a state machine having a plurality of states including an initial state and a final state with a set of transitions from the initial state to the final state. The transitions are triggered by the barometric signal reaching one or more triggering thresholds. The processing unit may include an expert system sensitive to state data and altitude data from the state machine for recognizing the final state being reached.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: A method of adjusting a lens may include adjusting the lens at a first focus position, and acquiring a first image of a scene through the lens. The method may further include adjusting the lens at a second focus position, and acquiring a second image of the same scene through the lens. In addition, the method may include producing respective power spectra of the first and second images, and producing a criterion representing the ratio of the power spectra to estimate a focus error of the lens.

Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.

Abstract: According to an embodiment, a waveform generator includes a phase accumulator configured to generate a digital phase signal representing a phase angle, and a phase-to-amplitude converter configured to receive the digital phase signal as a phase input, and generate sine and cosine waveform values as digital amplitude signals, wherein the phase-to-amplitude converter does not include a look-up table.

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Abstract: A hybrid analog-digital pixel circuit is fabricated on two wafers. A first wafer includes the analog pixel circuitry and a second wafer includes the digital control and processing circuitry. Externally accessible contact structures for electrically interconnecting the two wafers are arranged in groups. Each group includes externally accessible contact structures for carrying signals associated solely with operation of a corresponding pixel.

Abstract: A gas measurement device measures gas using a gas sensor including a sense resistance exposed to the gas and a reference resistance not exposed to the gas. The gas measurement device applies a first current value and a second current value to the sensor. A detector functions to detect a first resistance variation and a second resistance variation of the sense resistance exposed to the gas with respect to the reference resistance as a function of the first current value and the second current value, respectively. The resistance variation dependent on relative humidity is then determined as a function of the first and second resistance variations and a first constant. The resistance variation dependent on gas content is then determined as a function of the first and second resistance variations and a second (different) constant.