Abstract: Apparatus and methods to reduce effects of erratic motion input during operation of an instrument via a graphical user interface are described. Spatial motion input received from a user may be filtered using filter parameters obtained during a calibration procedure. The filtered motion input may be used to predict a trajectory of a cursor or object used to select an icon or text. The icon or text may be latched to the approaching cursor or object. The combination of motion smoothing and latching may improve ease-of-use of the graphical user interface for individuals having neuromuscular disorder, or users operating instruments in high-vibration environments.

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

Abstract: A digital representation of a waveform is generated based on signals received during a recording period. The received signals include a digital clock signal providing a determined number of clock pulses during the recording period, a plurality of binary digital signals defining, for each clock pulse of the determined number of clock pulses, a waveform state associated with the clock pulse. A digital representation of the waveform is generated and storing. The waveform has a duration based on the recording period and a profile based on the defined waveform states associated with the clock pulses of the determined number of clock pulses.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.

Abstract: A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Abstract: A driving module of a resonant converter receives an enabling signal and a voltage across a switch of a secondary side, and generates a control signal for first and second switches of the secondary side. The driving module cyclically controls switches of a primary full-bridge switching stage and both switches of the secondary side. After a fixed time, the driving module turns off the low-side switch and turns on the high-side switch, waits for a rising edge of the enabling signal, waits for zero current in the secondary side switches, turns off the first switch via the control signal after a variable delay relative to the rising edge of the enabling signal, keeps the second switch on, waits for zero voltage across the first switch, switches back on the first switch via the control signal when the voltage measured across the first switch drops below a variable threshold.

Abstract: A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.

Abstract: An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: Identical planar electronic components are stacked in an assembly. Each component has two contact metallizations positioned on edges of a same surface of the component. The components are stacked along a common axis. Each successive component is rotated about the common axis by a fixed angle. A value of the fixed angle is selected to position, side by side, the contact metallization of one component and the contact metallization of another next component adjacent to each other in the stack. Electrical connections are provided between two adjacent contact metallizations.

Abstract: A device disclosed herein includes a feedback measuring circuit to measure a signal flowing through a movable MEMS mirror. Processing circuitry determines a time at which the signal indicates that a capacitance of the movable MEMS mirror is substantially at a maximum capacitance. The processing circuitry also determines, over a window of time extending from the time at which the signal indicates that the capacitance of the movable MEMS mirror is substantially at the maximum to a given time, a total change in capacitance of the movable MEMS mirror compared to the maximum capacitance. The processor further determines the capacitance at the given time as a function of the total change in capacitance, and determines an opening angle of the movable MEMS mirror as a function of the capacitance at the given time.

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

Abstract: A semiconductor substrate includes a first portion and a second portion. The first portion of the substrate has a first deformation-stress sensor capable of supplying a first stress signal. The second portion of the substrate has a second deformation-stress sensor capable of supplying a second stress signal. The first stress signal and second stress signal are processed by a circuit to produce a compensation signal. The compensation signal is applied in feedback to one of the first and second stress signals to compensate for variations induced in said one of the first and second stress signals by stresses in the semiconductor substrate.

Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

Abstract: An amplifier circuit, for a capacitive acoustic transducer defining a sensing capacitor that generates a sensing signal as a function of an acoustic signal, has a first input terminal and a second input terminal, which are coupled to the sensing capacitor and: a dummy capacitor, which has a capacitance corresponding to a capacitance at rest of the sensing capacitor and a first terminal connected to the first input terminal; a first buffer amplifier, which is coupled at input to the second input terminal and defines a first differential output of the circuit; a second buffer amplifier, which is coupled at input to a second terminal of the dummy capacitor and defines a second differential output of the circuit; and a feedback stage, which is coupled between the differential outputs and the first input terminal, for feeding back onto the first input terminal a feedback signal, which has an amplitude that is a function of the sensing signal and is in phase opposition with respect thereto.

Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

Abstract: A microprocessor of a solid state memory protects the contents of the solid state memory by comparing a sequence of requests for access to physical blocks of the solid state memory with a predetermined sequence of requests to verify the sequence of requests, and by responding to additional requests for access to the physical blocks of the solid state memory to decrypt and transfer requested files stored therein when the sequence of requests equals the predetermined sequence of requests, thereby verifying the sequence of requests. The predetermined sequence of requests is associated with a plurality of virtual files that can be selected, in a particular sequence, to simulate a request for access to physical blocks of the solid state memory, while the predetermined sequence of requests is stored in a configuration file of the solid state memory in correspondence with an identifier of additional protected files.