Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.
Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.
Abstract: Multicast transmissions are efficient but do not allow for individual acknowledgement that the data was received by each receiver. This is not acceptable for isochronous systems that require specific levels of QoS for each device. A multimedia communications protocol is provided that uses a novel multi-destination burst transmission protocol in multimedia isochronous systems. The transmitter establishes a bi-directional burst mode for multicasting data to multiple devices and receiving Reverse Start of Frame (RSOF) delimiters from each multicast-destination receiver in response to multiple SOF delimiters, thus providing protocol-efficient multi-destination acknowledgements.
Type:
Application
Filed:
October 10, 2017
Publication date:
February 8, 2018
Applicant:
STMicroelectronics, Inc.
Inventors:
Oleg Logvinov, Aidan Cully, David Lawrence, Michael J. Macaluso
Abstract: A virtual memory is partitioned into virtual partitions, each partition being subdivided into virtual sub-partitions and each sub-partition corresponding to a combination of multiple sectors of identical or different sizes of a physical memory. When an allocation request is made for a virtual memory space having a given memory size, a free partition is selected, a virtual sub-partition is selected corresponding to a combination of sectors having a minimum total size covering the given memory size of the virtual memory to be allocated, and free sectors of the physical memory are selected corresponding to the selected combination. A determination is made of a correspondence table between the selected virtual partition and the initial physical addresses of the selected free sectors, and a virtual address is generated.
Abstract: An IC may include a semiconductor substrate having circuitry formed in the substrate, an interconnect layer above the semiconductor substrate and having an antenna coupled to the circuitry, and a seal ring around a periphery of the interconnect layer. The IC may include an electrically insulating trench extending vertically into the semiconductor substrate and extending laterally across the semiconductor substrate from adjacent one side to adjacent another side.
Type:
Grant
Filed:
December 10, 2014
Date of Patent:
February 6, 2018
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Alberto Pagani, Giovanni Girlando, Federico Giovanni Ziglioli, Alessandro Finocchiaro
Abstract: An electronic device may include a transducer configured to generate an electrical output responsive to an input, and a data storage element configured to change state responsive to the transducer. The electronic device may include a power circuit configured to turn on and supply power responsive to the data storage element changing state, and a processing circuit configured to be powered by the power circuit.
Abstract: An electronic device includes at least one laser source configured to direct laser radiation toward a user's hand. Laser detectors are configured to receive reflected laser radiation from the user's hand. A controller is coupled to the at least one laser source and laser detectors and configured to determine a set of distance values to the user's hand for each respective laser detector and based upon a time-of-flight of the laser radiation. The controller also determines a hand gesture from among a plurality of possible hand gestures based upon the sets of distance values using Bayesian probabilities.
Abstract: A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.
Abstract: A system includes an antenna, and communications circuitry coupled to the antenna and configured for at least one of receiving and transmitting information via the antenna based on a contactless communications protocol. A charger is configured for contactless charging a power supply module via the antenna. A controller is configured for selectively operating the communications circuitry and the charger.
Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
Type:
Grant
Filed:
December 29, 2014
Date of Patent:
February 6, 2018
Assignees:
INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
Abstract: An oscillating structure with piezoelectric actuation includes first and second torsional elastic elements constrained to respective portions of a fixed supporting body and defining an axis of rotation. A mobile element is positioned between, and connected to, the first and second torsional elastic elements by first and second rigid regions. A first control region is coupled to the first rigid region and includes a first piezoelectric actuator. A second control region is coupled to the second rigid region and includes a second piezoelectric actuator. The first and second piezoelectric actuators are configured to cause local deformation of the first and second control regions to induce a torsion of the first and second torsional elastic elements.
Abstract: A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.
Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.
Type:
Application
Filed:
March 16, 2017
Publication date:
February 1, 2018
Applicant:
STMicroelectronics (Crolles 2) SAS
Inventors:
Patrick Le Maitre, Jean-Francois Carpentier
Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.
Abstract: A receiver for digital signals includes a radiofrequency stage. A feedback loop controls a variable attenuation resistance applied to a modulated radiofrequency signal passing through the radiofrequency stage as a function of a comparison of an amplitude of the modulated radiofrequency signal with a reference value. A baseband stage includes an RC network cascaded to the radiofrequency stage and coupled to a baseband detector that generates the baseband signal. The feedback loop includes a circuit for detecting a range of variation of the comparison. The value of the variable resistance is controlled as a function of an end value (e.g., maximum or minimum) of the detected range of variation.
Type:
Application
Filed:
October 11, 2017
Publication date:
February 1, 2018
Applicant:
STMicroelectronics S.r.l.
Inventors:
Ranieri Guerra, Roberto Larosa, Giuseppe Palmisano
Abstract: An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.
Abstract: A buried cavity is formed in a monolithic body to delimit a suspended membrane. A peripheral insulating region defines a supporting frame in the suspended membrane. Trenches extending through the suspended membrane define a rotatable mobile mass carried by the supporting frame. The mobile mass forms an oscillating mass, supporting arms, spring portions, and mobile electrodes that are combfingered to fixed electrodes of the supporting frame. A reflecting region is formed on top of the oscillating mass.
Type:
Application
Filed:
March 21, 2017
Publication date:
February 1, 2018
Applicant:
STMicroelectronics S.r.l.
Inventors:
Enri Duqi, Lorenzo Baldo, Roberto Carminati, Flavio Francesco Villa
Abstract: A vertical conduction integrated electronic device including: a semiconductor body; a trench that extends through part of the semiconductor body and delimits a portion of the semiconductor body, which forms a first conduction region having a first type of conductivity and a body region having a second type of conductivity, which overlies the first conduction region; a gate region of conductive material, which extends within the trench; an insulation region of dielectric material, which extends within the trench and is arranged between the gate region and the body region; and a second conduction region, which overlies the body region. The second conduction region is formed by a conductor.
Type:
Grant
Filed:
May 26, 2017
Date of Patent:
January 30, 2018
Assignee:
STMicroelectronics S.r.l.
Inventors:
Davide Giuseppe Patti, Antonio Giuseppe Grimaldi
Abstract: Methods of forming micro-electromechanical device include a semiconductor substrate, in which a first microstructure and a second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the substrate so as to undergo equal strains as a result of thermal expansions of the substrate. Furthermore, the first microstructure is provided with movable parts and fixed parts with respect to the substrate, while the second microstructure has a shape that is substantially symmetrical to the first microstructure but is fixed with respect to the substrate. By subtracting the changes in electrical characteristics of the second microstructure from those of the first, variations in electrical characteristics of the first microstructure caused by changes in thermal expansion or contraction can be compensated for.
Type:
Grant
Filed:
May 6, 2014
Date of Patent:
January 30, 2018
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Ernesto Lasalandra, Angelo Merassi, Sarah Zerbini
Abstract: A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.