Patents Assigned to STMicroelectronics AS
  • SAMPLING FREQUENCY AND ACCUMULATOR SWEEPING IN A TOUCH SCREEN CONTROLLER
    Publication number: 20180046320
    Abstract: A circuit described herein includes a charge to voltage converter circuit having an input coupled to receive a sense signal from a sense node associated with a mutual capacitance to be sensed, and an output. A reset switch is coupled between the output of the charge to voltage converter circuit and the input of the charge to voltage converter. An accumulator circuit is configured to accumulate voltages at the output of the charge to voltage converter circuit and to generate an accumulator output signal. Control circuitry is configured to generate control signals for the reset switch and accumulator circuit so as to reduce noise in the accumulator output signal.
    Type: Application
    Filed: August 12, 2016
    Publication date: February 15, 2018
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hugo Gicquel, Chee Weng Cheong
  • GERMANIUM-ON-SILICON LASER IN CMOS TECHNOLOGY
    Publication number: 20180048123
    Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
    Type: Application
    Filed: March 6, 2015
    Publication date: February 15, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, Centre National de la Recherche Scientifique, Universite Paris SUD
    Inventors: Mathias Prost, Moustafa El Kurdi, Philippe Boucaud, Frederic Boeuf
  • CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES
    Publication number: 20180045775
    Abstract: An integrated circuit is fabricated on a semiconductor material die and adapted to be at least partly tested wirelessly. Circuitry for setting a selected radio communication frequency to be used for the wireless test of the integrated circuit is integrated on the semiconductor material die.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 15, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Circuit to implement a diode function
    Patent number: 9892877
    Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 13, 2018
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventors: Vratislav Michal, Denis Cottin
  • Fully substrate-isolated FinFET transistor
    Patent number: 9893147
    Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: February 13, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Prasanna Khare
  • System and method for a multistage operational amplifier
    Patent number: 9893689
    Abstract: According to an embodiment, an operational amplifier includes a first amplifier stage coupled between an input node and an intermediate node, a second amplifier stage coupled between the intermediate node and an output node, a compensation capacitor having a first terminal coupled to the intermediate node and a second terminal, and a compensation amplifier coupled between the output node and the second terminal. The compensation amplifier has a positive gain greater than one.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Riccardo Zurla, Alessandro Cabrini, Guido Torelli
  • Method and device for measuring electrical impedance of biologic tissues
    Patent number: 9888863
    Abstract: A device for measuring an electrical impedance of biologic tissue may include electrodes configured to contact the biologic tissue and generate a differential voltage thereon. The device may include a first circuit coupled to the electrodes and configured to force an oscillating input signal therethrough, and a differential amplitude modulation (AM) demodulator coupled to the plurality of electrodes. The differential AM demodulator may be configured to demodulate the differential voltage, and generate a base-band signal representative of the demodulated differential voltage. The device may further include an output circuit downstream from the differential AM demodulator and may be configured to generate an output signal representative of the electrical impedance as a function of the base-band signal.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 13, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Pasquale Biancolillo, Stefano Rossi, Giuseppe Bruno, Angelo Recchia
  • Integrated electro-optic modulator
    Patent number: 9891450
    Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles Baudot, Maurin Douix, Frédéric Boeuf, Sébastien Cremer
  • Device and method for controlling a voltage regulator and corresponding voltage regulator
    Patent number: 9893614
    Abstract: A method includes generating a control signal for controlling a switch element, and determining at each switching cycle alternation of an ON interval with storage of energy in the inductor element starting from an input voltage, and an OFF interval with transfer of the energy stored in an inductor element into a storage element on which an output voltage is present. The method includes when the inductor current reaches the first threshold value before the end of a first interval, determining the end of the ON interval at the end of the first interval. The method includes following detection of the ON interval having a duration equal to the first interval, the detection being indicative of a possible short-circuit condition at output, determining the OFF interval having a second duration equal to a lengthened interval longer than the first duration.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Donato Tagliavia, Calogero Andrea Trecarichi
  • Offset calibration circuit and method for an amplifier circuit
    Patent number: 9893688
    Abstract: A differential amplifier has an inherent offset voltage. In many circuit applications, such as with a voltage to current converter circuit, it is important to nullify that offset voltage. A calibration circuit is provided to configured the differential amplifier to operate as a comparator with a common voltage applied to both inputs. The logic state of the output of the amplifier indicates whether the offset voltage is positive or negative. In response thereto, a trim current with a progressively increasing magnitude is injected into the amplifier and the amplifier output is monitored to detect a change in logic state. The magnitude of the trim current at the point where the logic state changes is the magnitude of trim current needed to nullify the voltage offset.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventor: Pavan Nallamothu
  • Method for powering a module incorporated within a system-on-a-chip and corresponding electronic device
    Patent number: 9891637
    Abstract: A module incorporated within a system-on-a-chip operating in a steady-state power supply phase is powered by supplying to the module a regulated power supply voltage obtained from a feedback control loop. The receives a main power supply voltage and a negative feedback voltage. The negative feedback voltage is generated inside the system-on-a-chip starting from an effective supply voltage of the module and from a setpoint signal corresponding to a desired regulated power supply voltage.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Grand Ouest) SAS
    Inventor: Christophe Belet
  • NFC device with multiple secure elements
    Patent number: 9894469
    Abstract: An NFC device includes first and second secure elements, an NFC router, and a processor. A method involves emulating, by the NFC router in response to a command from the processing device, an RF card emulation transaction. The RF card emulation transaction includes transmitting by the NFC router a command to the first and second secure elements to verify the presence of NFC transaction applications in the first and second secure elements. The method also includes receiving, by the NFC router, responses from the first and second secure elements and a new RF message from an NFC terminal. The responses indicate the NFC transaction applications stored by the first and second secure elements, and the new RF message relates to an NFC transaction. The new RF message is routed to the first or second secure element based on the responses.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 13, 2018
    Assignees: Proton World International N.V., STMicroelectronics (Rousset) SAS
    Inventors: Olivier Van Nieuwenhuyze, Jean Marc Grimaud, Arach Mohammed Brahim
  • Temperature-compensated state of charge estimation for rechargeable batteries
    Patent number: 9891287
    Abstract: The remaining state of charge of a rechargeable battery is calculated by: measuring the instantaneous voltage, impedance and temperature of the battery, and then inputting the measured voltage, impedance and temperature values into an equation, wherein the equation yields a state of charge value that is a function of the said measured voltage, impedance and temperature values.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 13, 2018
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Daniel Ladret
  • Bidirectional voltage differentiator circuit
    Patent number: 9891250
    Abstract: A bidirectional voltage differentiator circuit comprises start-up circuitry, sensing circuitry, and output circuitry coupled to logic circuitry. The start-up circuitry acts to start-up the sensing circuitry when the circuit is powered on, and accelerates the response of the sensing circuitry thereafter. The sensing circuitry senses variation in an input voltage applied to an input node. Responsive to the voltage variation sensed by the sensing circuitry, the output circuitry produces a state change at a first or second output node. The logic circuitry receives the states of the output nodes and produces a logic output signal to indicate the occurrence of the variation sensed in the input voltage. The voltage sensing circuit is operable to sense variation of the input voltage regardless of whether the voltage is rising or falling and without regard to the DC value of the input voltage.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventor: Yijun Duan
  • Graphene based filler material of superior thermal conductivity for chip attachment in microstructure devices
    Patent number: 9892994
    Abstract: An integrated circuit chip attachment in a microstructure device is accomplished through the use of an adhesive-based material in which graphene flakes are incorporated. This results in superior thermal conductivity. The spatial orientation of the graphene flakes is controlled, for example by adhering polar molecules to the graphene flakes and exposing the flakes to an external force field, so that the graphene flakes have desired orientations under the integrated circuit chip, alongside of the integrated circuit chip and above the integrated circuit chip.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: February 13, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giovanni Scurati, Laura Ceriati, Luciano Benini
  • Managing IR drop
    Patent number: 9891279
    Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics International N.V.
    Inventor: Ajay Kumar Dimri
  • Integrated circuit power supply regulator
    Patent number: 9891639
    Abstract: The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Fabrice Marinet
  • Semiconductor device, corresponding methods of production and use and corresponding apparatus
    Patent number: 9893001
    Abstract: A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Arrigoni, Alberto Da Dalt
  • METHOD FOR ESTIMATING AN OPERATING PROFILE OF AN INTEGRATED CIRCUIT OF A SYSTEM-ON-A-CHIP, AND CORRESPONDING SYSTEM-ON-A-CHIP
    Publication number: 20180038907
    Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.
    Type: Application
    Filed: March 24, 2017
    Publication date: February 8, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Chittoor Parthasarathy
  • METHOD FOR ADJUSTING AT LEAST ONE OPERATING POINT OF AT LEAST ONE INTEGRATED CIRCUIT OF A SYSTEM ON A CHIP, AND CORRESPONDING SYSTEM ON A CHIP
    Publication number: 20180039320
    Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.
    Type: Application
    Filed: March 23, 2017
    Publication date: February 8, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy